00001 /* FreeEMS - the open source engine management system 00002 * 00003 * Copyright 2008, 2009 Fred Cooke 00004 * 00005 * This file is part of the FreeEMS project. 00006 * 00007 * FreeEMS software is free software: you can redistribute it and/or modify 00008 * it under the terms of the GNU General Public License as published by 00009 * the Free Software Foundation, either version 3 of the License, or 00010 * (at your option) any later version. 00011 * 00012 * FreeEMS software is distributed in the hope that it will be useful, 00013 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 * GNU General Public License for more details. 00016 * 00017 * You should have received a copy of the GNU General Public License 00018 * along with any FreeEMS software. If not, see http://www.gnu.org/licenses/ 00019 * 00020 * We ask that if you make any changes to this file you email them upstream to 00021 * us at admin(at)diyefi(dot)org or, even better, fork the code on github.com! 00022 * 00023 * Thank you for choosing FreeEMS to run your engine! 00024 */ 00025 00026 00040 #include "inc/freeEMS.h" 00041 #include "inc/interrupts.h" 00042 00043 00044 /* Correctly placed in memory due to compiler/linker directives in memory.x and the linker script. */ 00045 /* This is the FULL table of length 0xFF starting at 0xFF00 and ending at 0xFFFF, redirected with */ 00046 /* jumps to the offset location by the serial monitor starting at 0xF700 and ending at 0xF800 */ 00047 /* http://m68hc11.serveftp.org/wiki/index.php/FAQ:Interrupts */ 00048 const interruptTable _vectors[] VECTORS = { 00049 /* 0xFF00 to 0xFF0F */ 00050 /* The first row are NOT actually interrupts at all, just a wasted 16 bytes for tidiness */ 00051 /* UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, */ 00052 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00053 /* */ 00054 00055 /* 0xFF10 to 0xFF1F */ 00056 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00057 /* Spurious Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00058 /* */ 00059 00060 /* 0xFF20 to 0xFF2F */ 00061 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00062 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00063 /* */ 00064 00065 /* 0xFF30 to 0xFF3F */ 00066 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00067 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00068 /* */ 00069 00070 /* 0xFF40 to 0xFF4F */ 00071 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00072 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00073 /* */ 00074 00075 /* 0xFF50 to 0xFF5F */ 00076 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00077 /* Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved */ 00078 /* */ 00079 00080 /* 0xFF60 to 0xFF6F */ 00081 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00082 /* RAM violation XGATEsoft error XGATE 7 XGATE 6 XGATE 5 XGATE 4 XGATE 3 XGATE 2 */ 00083 /* */ 00084 00085 /* 0xFF70 to 0xFF7F */ 00086 UISR, UISR, StagedOffISR, StagedOnISR, IgnitionFireISR,IgnitionDwellISR,UISR, UISR,//VRegAPIISR, 00087 /* XGATE 1 XGATE 0 PIT 3 PIT 2 PIT 1 PIT 0 Reserved API */ 00088 /* Fire Coil Dwell Coil */ 00089 00090 /* 0xFF80 to 0xFF8F */ 00091 LowVoltageISR, UISR, UISR, UISR, UISR, UISR, UISR, PortPISR, 00092 /* Low Voltage IIC1 SCI5 SCI4 SCI3 SCI2 PWM ESDown Port P */ 00093 /* */ 00094 00095 /* 0xFF90 to 0xFF9F */ 00096 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00097 /* CAN4 Tx CAN4 Rx CAN4 Errors CAN4 Wakeup CAN3 Tx CAN3 Rx CAN3 Errors CAN3 Wakeup */ 00098 /* */ 00099 00100 /* 0xFFA0 to 0xFFAF */ 00101 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00102 /* CAN2 Tx CAN2 Rx CAN2 Errors CAN2 Wakeup CAN1 Tx CAN1 Rx CAN1 Errors CAN1 Wakeup */ 00103 /* */ 00104 00105 /* 0xFFB0 to 0xFFBF */ 00106 UISR, UISR, UISR, UISR, UISR, UISR, UISR, UISR, 00107 /* CAN0 Tx CAN0 Rx CAN0 Errors CAN0 Wakeup FLASH EEPROM SPI2 SPI1 */ 00108 /* */ 00109 00110 /* 0xFFC0 to 0xFFCF */ 00111 UISR, UISR, UISR, UISR, UISR, ModDownCtrISR, PortHISR, PortJISR, 00112 /* IIC0 Reserved CRG self clock CRG PLL lock PAB Overflow ModDwnCtrUF Port H Port J */ 00113 /* */ 00114 00115 /* 0xFFD0 to 0xFFDF */ 00116 UISR, UISR, UISR, SCI0ISR, UISR, UISR, UISR, TimerOverflow, 00117 /* ATD1 ATD0? SCI1 SCI0 SPI0 PAIE PAA OF ECT OF */ 00118 /* Serial 0 */ 00119 00120 /* 0xFFE0 to 0xFFEF */ 00121 Injector6ISR, Injector5ISR, Injector4ISR, Injector3ISR, Injector2ISR, Injector1ISR, SecondaryRPMISR,PrimaryRPMISR, 00122 /* ECT7 ECT6 ECT5 ECT4 ECT3 ECT2 ECT1 ECT0 */ 00123 /* Injector 6 Injector 5 Injector 4 Injector 3 Injector 2 Injector 1 Secondary RPM Primary RPM */ 00124 00125 /* 0xFFF0 to 0xFFFF */ 00126 RTIISR, IRQISR, XIRQISR, UISR, UISR, UISR, UISR, _start 00127 /* RTI IRQ XIRQ SWI UnimpInstruct COP Reset ClockReset SystemReset */ 00128 /* Entry point */ 00129 };
1.6.3