00001 /* FreeEMS - the open source engine management system 00002 * 00003 * Copyright 2008, 2009 Fred Cooke 00004 * 00005 * This file is part of the FreeEMS project. 00006 * 00007 * FreeEMS software is free software: you can redistribute it and/or modify 00008 * it under the terms of the GNU General Public License as published by 00009 * the Free Software Foundation, either version 3 of the License, or 00010 * (at your option) any later version. 00011 * 00012 * FreeEMS software is distributed in the hope that it will be useful, 00013 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 * GNU General Public License for more details. 00016 * 00017 * You should have received a copy of the GNU General Public License 00018 * along with any FreeEMS software. If not, see http://www.gnu.org/licenses/ 00019 * 00020 * We ask that if you make any changes to this file you email them upstream to 00021 * us at admin(at)diyefi(dot)org or, even better, fork the code on github.com! 00022 * 00023 * Thank you for choosing FreeEMS to run your engine! 00024 */ 00025 00026 00043 /* see if we've seen this, if not, mark seen and process */ 00044 #ifndef FILE_9S12XDP512_H_SEEN 00045 #define FILE_9S12XDP512_H_SEEN 00046 00047 00048 /* shortcuts to speed formatting */ 00049 /* www.atmel.com/dyn/resources/prod_documents/avr_3_04.pdf First page, second column */ 00050 /* http://www.ee.nmt.edu/~rison/ee308_spr06/homepage.html */ 00051 /* extra parentheses for clarity and guarantee of precedence */ 00052 00053 /* Dereferenced Volatile Unsigned Char Pointer */ 00054 #define DVUCP(address) (*((volatile unsigned char*)(address))) 00055 /* Dereferenced Volatile Unsigned Short Pointer */ 00056 #define DVUSP(address) (*((volatile unsigned short*)(address))) 00057 00058 /* Address Volatile Unsigned Char Pointer */ 00059 #define AVUCP(address) ((volatile unsigned char*)(address)) 00060 /* Address Volatile Unsigned Short Pointer */ 00061 #define AVUSP(address) ((volatile unsigned short*)(address)) 00062 00063 00064 00065 /* Port Integration Module - Reordered within sections for clarity */ 00066 /* PIM information from 5 tables the last of which is spread over three pages */ 00067 00068 /* Plain ports output switch, input state registers */ 00069 #define PORTS_BA DVUSP(0x0001) /* Both A and B combined as a 16 bit register for ignition access */ 00070 #define PORTA DVUCP(0x0000) 00071 #define PORTB DVUCP(0x0001) 00072 #define PORTE DVUCP(0x0008) 00073 #define PORTK DVUCP(0x0032) 00074 /* #define PORTC DVUCP(0x0004) these pins are not bonded on the 112 pin package */ 00075 /* #define PORTD DVUCP(0x0005) these pins are not bonded on the 112 pin package */ 00076 00077 00078 /* Plain ports Data Direction Registers */ 00079 #define DDRA DVUCP(0x0002) 00080 #define DDRB DVUCP(0x0003) 00081 #define DDRE DVUCP(0x0009) 00082 #define DDRK DVUCP(0x0033) 00083 00084 00085 #define DDRC DVUCP(0x0006) /* these pins are not bonded on the 112 pin package but need switching to output */ 00086 #define DDRD DVUCP(0x0007) /* these pins are not bonded on the 112 pin package but need switching to output */ 00087 00088 00089 /* 0b1//1//00 */ 00090 /* --K//E//BA */ 00091 /* TODO NOTE: the sixth bit controls pull up on BKGD and VREGEN pins set this to ???? */ 00092 /* NOTE: pull up on port E is for 0-4 and 7, ports 5 and 6 are pulled down during reset and never pulled up. */ 00093 #define PUCR DVUCP(0x000C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00094 00095 00096 /* 0b1//0//00 */ 00097 /* --K//E//BA */ 00098 /* NOTE: reduced drive affects all pins of all ports listed above. */ 00099 #define RDRIV DVUCP(0x000D) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00100 00101 00102 #define ECLKCTL DVUCP(0x001C) /* Comes up 0b_1100_0000 = both pins off in normal single chip mode */ 00103 #define IRQCR DVUCP(0x001E) /* 0 in bit 7 makes it ultra sensitive, 1 makes it falling edge sensitive. 0 in bit 6 turns interrupts off, 1 in bit 6 turns them on. */ 00104 00105 00106 /* Port T registers */ 00107 #define PTT DVUCP(0x0240) /* GPIO output register, can not be read from reliably, use PTIT instead */ 00108 #define PORTT DVUCP(0x0240) /* Duplicate definition for consistency */ 00109 #define PTIT DVUCP(0x0241) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00110 #define DDRT DVUCP(0x0242) /* TODO configure all IO as outputs until we need it */ 00111 #define RDRT DVUCP(0x0243) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00112 #define PERT DVUCP(0x0244) /* pull up/down enable when used as an input, 0 = no pull up, 1 = pull up on */ 00113 #define PPST DVUCP(0x0245) /* 0 = pull up, 1 = pull down */ 00114 00115 00116 /* Port S registers */ 00117 #define PTS DVUCP(0x0248) 00118 #define PORTS DVUCP(0x0248) /* Duplicate definition for consistency */ 00119 #define PTIS DVUCP(0x0249) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00120 #define DDRS DVUCP(0x024A) /* TODO configure all IO as outputs until we need it */ 00121 #define RDRS DVUCP(0x024B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00122 #define PERS DVUCP(0x024C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00123 #define PPSS DVUCP(0x024D) /* 0 = pull up, 1 = pull down */ 00124 #define WOMS DVUCP(0x024E) /* wired OR mode TODO find out what this actually means in real terms. */ 00125 00126 00127 /* Port M registers */ 00128 #define PTM DVUCP(0x0250) 00129 #define PORTM DVUCP(0x0250) /* Duplicate definition for consistency */ 00130 #define PTIM DVUCP(0x0251) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00131 #define DDRM DVUCP(0x0252) /* TODO configure all IO as outputs until we need it */ 00132 #define RDRM DVUCP(0x0253) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00133 #define PERM DVUCP(0x0254) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00134 #define PPSM DVUCP(0x0255) /* 0 = pull up, 1 = pull down */ 00135 #define WOMM DVUCP(0x0256) /* wired OR mode TODO find out what this actually means in real terms. */ 00136 00137 00138 /* this should be set to the following bit mask xx????00 */ 00139 #define MODRR DVUCP(0x0257) 00140 00141 00142 /* Port P registers */ 00143 #define PTP DVUCP(0x0258) 00144 #define PORTP DVUCP(0x0258) /* Duplicate definition for consistency */ 00145 #define PTIP DVUCP(0x0259) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00146 #define DDRP DVUCP(0x025A) /* TODO configure all IO as outputs until we need it */ 00147 #define RDRP DVUCP(0x025B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00148 #define PERP DVUCP(0x025C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00149 #define PPSP DVUCP(0x025D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00150 #define PIEP DVUCP(0x025E) /* interrupt enable, turns on interrupts */ 00151 #define PIFP DVUCP(0x025F) /* interrupt flag, write a 1 to clear it */ 00152 00153 00154 /* Port H registers */ 00155 #define PTH DVUCP(0x0260) 00156 #define PORTH DVUCP(0x0260) /* Duplicate definition for consistency */ 00157 #define PTIH DVUCP(0x0261) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00158 #define DDRH DVUCP(0x0262) /* TODO configure all IO as outputs until we need it */ 00159 #define RDRH DVUCP(0x0263) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00160 #define PERH DVUCP(0x0264) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00161 #define PPSH DVUCP(0x0265) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00162 #define PIEH DVUCP(0x0266) /* interrupt enable, turns on interrupts */ 00163 #define PIFH DVUCP(0x0267) /* interrupt flag, write a 1 to clear it */ 00164 00165 00166 /* Port J registers */ 00167 #define PTJ DVUCP(0x0268) 00168 #define PORTJ DVUCP(0x0268) /* Duplicate definition for consistency */ 00169 #define PTIJ DVUCP(0x0269) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */ 00170 #define DDRJ DVUCP(0x026A) /* TODO configure all IO as outputs until we need it */ 00171 #define RDRJ DVUCP(0x026B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00172 #define PERJ DVUCP(0x026C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00173 #define PPSJ DVUCP(0x026D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */ 00174 #define PIEJ DVUCP(0x026E) /* interrupt enable, turns on interrupts */ 00175 #define PIFJ DVUCP(0x026F) /* interrupt flag, write a 1 to clear it */ 00176 00177 00178 /* #define ATD0PT1 DVUCP(0x0271) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */ 00179 /* #define ATD0DDR1 DVUCP(0x0273) for use as an input, ATD0DIEN has to be set to 1. for use as an output? */ 00180 /* #define ATD0RDR1 DVUCP(0x0275) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00181 #define ATD0PER1 DVUCP(0x0277) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00182 00183 /* #define ATD1PT1 DVUCP(0x0279) we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */ 00184 /* #define ATD1DDR1 DVUCP(0x027B) for use as an input, ATD1DIEN1 has to be set to 1. for use as an output? */ 00185 /* #define ATD1RDR1 DVUCP(0x027D) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */ 00186 /* #define ATD1PER1 DVUCP(0x027F) pull up enable when used as an input, 0 = no pull up, 1 = pull up on */ 00187 00188 /* Not available on 112 pin version */ 00189 /* #define ATD1DDR0 DVUCP(0x027A) */ 00190 /* 0x0278 #define ATD1PT0 DVUCP() */ 00191 /* 0x027C #define ATD1RDR0 DVUCP() */ 00192 /* 0x027E #define ATD1PER0 DVUCP() */ 00193 00194 00195 /* Memory Mapping Control registers TODO configure these to suit our application. */ 00196 /* MMC 1/4 */ 00197 //0x000B MODE DVUCP() 00198 //0x000A MMCCTL0 DVUCP() 00199 //0x0013 MMCCTL1 DVUCP() 00200 00201 00202 /* Page control registers */ 00203 #define RPAGE DVUCP(0x0016) /* Used to page table data in and out of visible memory. */ 00204 //0x0017 EPAGE DVUCP() /* /* TODO similar to above if we need another 2k of eeprom. what are advantages/disadvantages of eeprom over flash?? */ 00205 #define PPAGE DVUCP(0x0030) /* TODO look at the best way to use the flash space in a complete system with a lot of code and data. used by compiler and maybe us to switch flash pages for loading/unloading data. */ 00206 //0x0010 GPAGE DVUCP() /* /* Global page register for global instruction addressing. I doubt we will use this. */ 00207 //0x0011 DIRECT DVUCP() /* /* Direct addressing mode control register. I doubt we will use this. */ 00208 00209 00211 //0x011C RAMWPC /* RAM Write Protection register, the pdf document appears to be incorrect for this, best not to touch it. */ 00212 //0x011D RAMXGU /* XGATE Upper region limit, this defines how much RAM we give the xgate to work with. */ 00213 //0x011E RAMSHL /* Shared memory lower boundary register, this defines the lower limit of the overlap between XGATE RAM and CPU RAM */ 00214 //0x011F RAMSHU /* Shared memory upper boundary register, this defines the upper limit of the overlap between XGATE RAM and CPU RAM */ 00215 00216 00218 //0x000E EBICTL0 DVUCP() /* 00219 //0x000F EBICTL1 DVUCP() /* 00220 00221 00223 //0x001A PARTIDH DVUCP() /* 00224 //0x001B PARTIDL DVUCP() /* 00225 00226 00227 /* Clock and Reset Generator */ 00228 #define SYNR DVUCP(0x0034) /* Multiplier of result of division by REFDV below, output is new PLL/Bus freqency. */ 00229 #define REFDV DVUCP(0x0035) /* Divisor of external clock frequency pre being multiplied by SYNR above. */ 00230 //0x0036 CTFLG DVUCP() /* 00231 #define CRGFLG DVUCP(0x0037) /* Clock and Reset Generator flags, we use this to determine when the PLL is stable and ready to use. Also to reset the RTI flag. */ 00232 #define CRGINT DVUCP(0x0038) /* Bit 7 is RTIE RTI enable bit. */ 00233 #define CLKSEL DVUCP(0x0039) /* Clock select register, choose PLL or external clock with this. */ 00234 #define PLLCTL DVUCP(0x003A) /* PLL frequency generator control register, used for setting the bus frequency. */ 00235 #define RTICTL DVUCP(0x003B) /* Divider select register */ 00236 #define COPCTL DVUCP(0x003C) /* COP watch dog control register */ 00237 //0x003D FORBYP DVUCP() /* 00238 #define ARMCOP DVUCP(0x003F) /* Computer operating properly timer, we won't be using this at least until we have profiled the running application. it will just cause headaches otherwise. */ 00239 00240 00241 /* Enhanced Capture Timer */ 00242 /* see reference document from Huang course overview/notes : http://www.ee.nmt.edu/~rison/ee308_spr06/lectures.html */ 00243 /* see this link for a discussion of the old 68hc12 timer http://www.seattlerobotics.org/encoder/nov97/68hc12.html */ 00244 00245 #define TCNT DVUSP(0x0044) /* Timer counter 16 bit (0x0044 TCNT (hi), 0x0045 TCNT (lo)) */ 00246 00247 /* Behavioural control registers (dual purpose) */ 00248 #define TIOS DVUCP(0x0040) /* Selects input capture or output compare mode for each timer pin */ 00249 #define TIE DVUCP(0x004C) /* Timer channel interrupt enable register */ 00250 #define TSCR1 DVUCP(0x0046) /* Timer System Control Register 1 */ 00251 #define TSCR2 DVUCP(0x004D) /* Timer System Control Register 2 */ 00252 #define TFLG DVUCP(0x004E) /* Timer channel flags */ 00253 #define TFLGOF DVUCP(0x004F) /* Timer over flow flag */ 00254 #define PTPSR DVUCP(0x006E) /* Precision prescaler for the main timer */ 00255 00256 /* Output compare control registers */ 00257 #define TTOV DVUCP(0x0047) /* Timer Toggle on Overflow output compare control */ 00258 #define CFORC DVUCP(0x0041) /* Output compare force, write a 1 to make the programmed action occur now */ 00259 #define OC7M DVUCP(0x0042) /* Channel 7 output compare other pins control mask */ 00260 #define OC7D DVUCP(0x0043) /* Channel 7 output compare other pins states */ 00261 00262 /* Timer output compare action control registers 00263 * OMx OLx Action 00264 * 0 0 Timer disconnected from output pin logic 00265 * 0 1 Toggle OCx output line 00266 * 1 0 Clear OCx output line to zero 00267 * 1 1 Set OCx output line to one */ 00268 #define TCTL1 DVUCP(0x0048) /* (M,L) 77,66,55,44 */ 00269 #define TCTL2 DVUCP(0x0049) /* (M,L) 33,22,11,00 */ 00270 #define TCTL1_ADDR AVUCP(0x0048) /* (M,L) 77,66,55,44 */ 00271 #define TCTL2_ADDR AVUCP(0x0049) /* (M,L) 33,22,11,00 */ 00272 00273 00274 /* Input capture control registers */ 00275 #define DLYCT DVUCP(0x0069) /* Delay counter control register (minimum tooth width) */ 00276 #define ICSYS DVUCP(0x006B) /* Input capture behaviour control register */ 00277 #define ICOVW DVUCP(0x006A) /* Input capture overwrite allow */ 00278 00279 /* Timer input capture edge detection control registers 00280 * EDGxB EDGxA Configuration 00281 * 0 0 Capture disabled 00282 * 0 1 Capture on rising edges only 00283 * 1 0 Capture on falling edges only 00284 * 1 1 Capture on any edge (rising or falling) */ 00285 #define TCTL3 DVUCP(0x004A) /* (B,A) 77,66,55,44 */ 00286 #define TCTL4 DVUCP(0x004B) /* (B,A) 33,22,11,00 */ 00287 00288 /* Input capture holding registers for 0 - 3 */ 00289 #define TC0H DVUSP(0x0078) /* 16 bit (0x0078 TC0H (hi), 0x0079 TC0H (lo)) */ 00290 #define TC1H DVUSP(0x007A) /* 16 bit (0x007A TC1H (hi), 0x007B TC1H (lo)) */ 00291 #define TC2H DVUSP(0x007C) /* 16 bit (0x007C TC2H (hi), 0x007D TC2H (lo)) */ 00292 #define TC3H DVUSP(0x007E) /* 16 bit (0x007E TC3H (hi), 0x007F TC3H (lo)) */ 00293 00294 /* Time value comparison/storage registers for each timer channel */ 00295 #define TC0 DVUSP(0x0050) /* 16 bit (0x0050 TC0 (hi), 0x0051 TC0 (lo)) */ 00296 #define TC1 DVUSP(0x0052) /* 16 bit (0x0052 TC1 (hi), 0x0053 TC1 (lo)) */ 00297 #define TC2 DVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */ 00298 #define TC3 DVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */ 00299 #define TC4 DVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */ 00300 #define TC5 DVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */ 00301 #define TC6 DVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */ 00302 #define TC7 DVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */ 00303 00304 #define TC2_ADDR AVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */ 00305 #define TC3_ADDR AVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */ 00306 #define TC4_ADDR AVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */ 00307 #define TC5_ADDR AVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */ 00308 #define TC6_ADDR AVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */ 00309 #define TC7_ADDR AVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */ 00310 00311 00312 00313 /* Pulse accumulator control registers */ 00314 #define ICPAR DVUCP(0x0068) 00315 /* (PACTL) 7 6 5 4 3 2 1 0 00316 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI */ 00317 #define PACTL DVUCP(0x0060) 00318 #define PAFLG DVUCP(0x0061) 00319 #define PBCTL DVUCP(0x0070) 00320 #define PBFLG DVUCP(0x0071) 00321 /* Pulse accumulator count registers dual access, 8 or 16 bit */ 00322 #define PACNUS2 DVUSP(0x0062) /* 16 bit (0x0062 PACN3, 0x0063 PACN2) */ 00323 #define PACNUS0 DVUSP(0x0064) /* 16 bit (0x0064 PACN1, 0x0065 PACN0) */ 00324 #define PACN3 DVUCP(0x0062) /* high */ 00325 #define PACN2 DVUCP(0x0063) /* low */ 00326 #define PACN1 DVUCP(0x0064) /* high */ 00327 #define PACN0 DVUCP(0x0065) /* low */ 00328 /* Pulse accumulator holding registers dual access, 8 or 16 bit */ 00329 #define PACHUS2 DVUSP(0x0072) /* 16 bit (0x0072 PACH3, 0x0073 PACH2) */ 00330 #define PACHUS0 DVUSP(0x0074) /* 16 bit (0x0074 PACH1, 0x0075 PACH0) */ 00331 #define PA3H DVUCP(0x0072) /* high */ 00332 #define PA2H DVUCP(0x0073) /* low */ 00333 #define PA1H DVUCP(0x0074) /* high */ 00334 #define PA0H DVUCP(0x0075) /* low */ 00335 00336 00337 /* Modulus down counter control registers */ 00338 #define MCCTL DVUCP(0x0066) /* Modulus control register */ 00339 #define MCFLG DVUCP(0x0067) /* Modulus flag (high bit) and input edge indicators (low 4 bits) */ 00340 #define MCCNT DVUSP(0x0076) /* 16 bit (0x0076 MCCNT (hi), 0x0077 MCCNT (lo)) */ 00341 #define PTMCPSR DVUCP(0x006F) /* Precision prescaler for the modulus down counter */ 00342 00343 00344 /* Analog To Digital converter 1 */ 00345 /* TODO Configure these and disable the non functional 16 - 23 144 pin section! */ 00346 #define ATD1CTL0 DVUCP(0x0080) /* 0 - 3 define which ADC channel to wrap on when doing multiple channels */ 00347 #define ATD1CTL1 DVUCP(0x0081) /* External trigger select when enabled in other control register */ 00348 #define ATD1CTL2 DVUCP(0x0082) /* bit 7 turns the ADC block on. */ 00349 #define ATD1CTL3 DVUCP(0x0083) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */ 00350 #define ATD1CTL4 DVUCP(0x0084) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */ 00351 #define ATD1CTL5 DVUCP(0x0085) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */ 00352 //0x0086 ATD1STAT0 DVUCP() /* 00353 //0x0088 ATD1TEST0 DVUCP() /* 00354 //0x0089 ATD1TEST1 DVUCP() /* 00355 //0x008A ATD1STAT2 DVUCP() /* 00356 //0x008B ATD1STAT1 DVUCP() /* 00357 #define ATD1DIEN0 DVUCP(0x008C) /* Digital input enable - these pins are not bonded on the 112 pin package */ 00358 #define ATD1DIEN1 DVUCP(0x008D) /* Digital input enable */ 00359 //0x008E ATD1PTAD0 DVUCP() /* digital use only */ 00360 //0x008F ATD1PTAD1 DVUCP() /* digital use only */ 00361 // one short for each hi lo par based on hi address. label with WORD for consistency 00362 #define ATD1_BASE 0x0090 00363 #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ /* SpareADC (NC) */ 00364 #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ /* SpareADC (NC) */ 00365 #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ /* SpareADC (NC) */ 00366 #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ /* SpareADC (NC) */ 00367 #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ /* SpareADC (NC) */ 00368 #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ /* SpareADC (NC) */ 00369 #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ /* SpareADC (NC) */ 00370 #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ /* SpareADC (NC) */ 00371 00372 00373 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */ 00374 //0x00A0 ATD1DR8H 00375 //0x00A1 ATD1DR8L 00376 //0x00A2 ATD1DR9H 00377 //0x00A3 ATD1DR9L 00378 //0x00A4 ATD1DR10H 00379 //0x00A5 ATD1DR10L 00380 //0x00A6 ATD1DR11H 00381 //0x00A7 ATD1DR11L 00382 //0x00A8 ATD1DR12H 00383 //0x00A9 ATD1DR12L 00384 //0x00AA ATD1DR13H 00385 //0x00AB ATD1DR13L 00386 //0x00AC ATD1DR14H 00387 //0x00AD ATD1DR14L 00388 //0x00AE ATD1DR15H 00389 //0x00AF ATD1DR15L 00390 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */ 00391 00392 00393 /* IIC1 - Inter Intergrated Circuit interface 1 TODO configure and use */ 00394 //0x00B0 IBAD DVUCP() /* 00395 //0x00B1 IBFD DVUCP() /* 00396 //0x00B2 IBCR DVUCP() /* 00397 //0x00B3 IBSR DVUCP() /* 00398 //0x00B4 IBDR DVUCP() /* 00399 00400 00401 /* SCI2 */ 00402 //0x00B8 SCI2BDH 00403 //0x00B8 SCI2ASR1 00404 //0x00B9 SCI2BDL 00405 //0x00B9 SCI2ACR1 00406 //0x00BA SCI2CR1 00407 //0x00BA SCI2ACR2 00408 //0x00BB SCI2CR2 00409 //0x00BC SCI2SR1 00410 //0x00BD SCI2SR2 00411 //0x00BE SCI2DRH 00412 //0x00BF SCI2DRL 00413 00414 00415 /* SCI3 */ 00416 //0x00C0 SCI3BDH 00417 //0x00C0 SCI3ASR1 00418 //0x00C1 SCI3BDL 00419 //0x00C1 SCI3ACR1 00420 //0x00C2 SCI3CR1 00421 //0x00C2 SCI3ACR2 00422 //0x00C3 SCI3CR2 00423 //0x00C4 SCI3SR1 00424 //0x00C5 SCI3SR2 00425 //0x00C6 SCI3DRH 00426 //0x00C7 SCI3DRL 00427 00428 00429 /* SCI0 debug/comms/datalogging TODO this is our primary serial interface for flash loading, setup serial comms software to communicate with MTX or similar for testing. */ 00430 #define SCI0_BASE 0x00C8 00431 00432 #define SCI0BD DVUSP(SCI0_BASE + 0x0) /* #define SCI0BDH DVUCP(0x00C8), #define SCI0BDL DVUCP(0x00C9) (IR and baud control) */ 00433 #define SCI0CR1 DVUCP(SCI0_BASE + 0x2) /* Control reg 1 */ 00434 00435 #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) /* Status reg 1a (rx flags) */ 00436 #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) /* Control reg 1a (rx conf) */ 00437 #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) /* Control reg 2a (rx conf) */ 00438 00439 #define SCI0CR2 DVUCP(SCI0_BASE + 0x3) /* Control reg 2 */ 00440 #define SCI0SR1 DVUCP(SCI0_BASE + 0x4) /* Status reg 1 (isr flags) */ 00441 #define SCI0SR2 DVUCP(SCI0_BASE + 0x5) /* Status reg 2 (config/control) */ 00442 #define SCI0DRH DVUCP(SCI0_BASE + 0x6) /* Data reg high (9th bit bit 7 receive bit 6 send) */ 00443 #define SCI0DRL DVUCP(SCI0_BASE + 0x7) /* Data reg low (read and write for receive and send respectively)*/ 00444 00445 00446 /* SCI1 debug/comms/datalogging TODO this is our secondary serial interface, setup serial comms software to communicate with MTX or similar for testing. */ 00447 //0x00D0 SCI1BDH 00448 //0x00D1 SCI1BDL 00449 //0x00D2 SCI1CR1 00450 00451 //0x00D0 SCI1ASR1 00452 //0x00D1 SCI1ACR1 00453 //0x00D2 SCI1ACR2 00454 00455 //0x00D3 SCI1CR2 00456 //0x00D4 SCI1SR1 00457 //0x00D5 SCI1SR2 00458 //0x00D6 SCI1DRH 00459 //0x00D7 SCI1DRL 00460 00461 00462 /* SPI0 */ 00463 //0x00D8 SPI0CR1 00464 //0x00D9 SPI0CR2 00465 //0x00DA SPI0BR 00466 //0x00DB SPI0SR 00467 //0x00DD SPI0DR 00468 00469 00470 /* IIC0 */ 00471 //0x00E0 IBAD 00472 //0x00E1 IBFD 00473 //0x00E2 IBCR 00474 //0x00E3 IBSR 00475 //0x00E4 IBDR 00476 00477 00478 /* SPI1 */ 00479 //0x00F0 SPI1CR1 00480 //0x00F1 SPI1CR2 00481 //0x00F2 SPI1BR 00482 //0x00F3 SPI1SR 00483 //0x00F5 SPI1DR 00484 00485 00486 /* SPI2 */ 00487 //0x00F8 SPI2CR1 00488 //0x00F9 SPI2CR2 00489 //0x00FA SPI2BR 00490 //0x00FB SPI2SR 00491 //0x00FD SPI2DR 00492 00493 00494 /* Flash Control Registers */ 00495 #define FCLKDIV DVUCP(0x0100) /* Flash Clock Divider Register R/W */ 00496 #define FSEC DVUCP(0x0101) /* Flash Security Register R */ 00497 #define FCNFG DVUCP(0x0103) /* Flash Configuration Register R/W */ 00498 #define FPROT DVUCP(0x0104) /* Flash Protection Register R/W */ 00499 #define FSTAT DVUCP(0x0105) /* Flash Status Register R/W */ 00500 #define FCMD DVUCP(0x0106) /* Flash Command Register R/W */ 00501 #define FCTL DVUCP(0x0107) /* Flash Control Register R */ 00502 00503 #define FADDR DVUSP(0x0108) /* Flash Low Address Register R (0x0108 FADDRHI, 0x0109 FADDRLO) */ 00504 #define FDATA DVUSP(0x010A) /* Flash High Data Register R (0x010A FDATAHI, 0x010B FDATALO) */ 00505 00506 00507 /* EEPROM Control Registers TODO learn how to use these to write data to the eeprom through serial comms. */ 00508 //0x0110 ECLKDIV 00509 //0x0113 ECNFG 00510 //0x0114 EPROT 00511 //0x0115 ESTAT 00512 //0x0116 ECMD 00513 //0x0118 EADDRHI 00514 //0x0119 EADDRLO 00515 //0x011A EDATAHI 00516 //0x011B EDATALO 00517 00518 00520 #define IVBR DVUCP(0x0121) /* Interrupt vector table base location first byte (second is always 0x00) */ 00521 #define INT_XGPRIO DVUCP(0x0126) 00522 #define INT_CFADDR DVUCP(0x0127) 00523 #define INT_CFDATA0 DVUCP(0x0128) 00524 #define INT_CFDATA1 DVUCP(0x0129) 00525 #define INT_CFDATA2 DVUCP(0x012A) 00526 #define INT_CFDATA3 DVUCP(0x012B) 00527 #define INT_CFDATA4 DVUCP(0x012C) 00528 #define INT_CFDATA5 DVUCP(0x012D) 00529 #define INT_CFDATA6 DVUCP(0x012E) 00530 #define INT_CFDATA7 DVUCP(0x012F) 00531 00532 00533 /* SCI4 */ 00534 //0x0130 SCI4BDH 00535 //0x0130 SCI4ASR1 00536 //0x0131 SCI4BDL 00537 //0x0131 SCI4ACR1 00538 //0x0132 SCI4CR1 00539 //0x0132 SCI4ACR2 00540 //0x0133 SCI4CR2 00541 //0x0134 SCI4SR1 00542 //0x0135 SCI4SR2 00543 //0x0136 SCI4DRH 00544 //0x0137 SCI4DRL 00545 00546 00547 /* SCI5 */ 00548 //0x0138 SCI5BDH 00549 //0x0138 SCI5ASR1 00550 //0x0139 SCI5BDL 00551 //0x0139 SCI5ACR1 00552 //0x013A SCI5CR1 00553 //0x013A SCI5ACR2 00554 //0x013B SCI5CR2 00555 //0x013C SCI5SR1 00556 //0x013D SCI5SR2 00557 //0x013E SCI5DRH 00558 //0x013F SCI5DRL 00559 00560 00561 /* CAN0 don't want this for now, leave it disabled too. CAN0CTL1 bit 7 should be set to zero to disable this. */ 00562 //0x0140 CAN0CTL0 00563 #define CAN0CTL1 DVUCP(0x0141) 00564 //0x0142 CAN0BTR0 00565 //0x0143 CAN0BTR1 00566 //0x0144 CAN0RFLG 00567 //0x0145 CAN0RIER 00568 //0x0146 CAN0TFLG 00569 //0x0147 CAN0TIER 00570 //0x0148 CAN0TARQ 00571 //0x0149 CAN0TAAK 00572 //0x014A CAN0TBSEL 00573 //0x014B CAN0IDAC 00574 //0x014D CAN0MISC 00575 //0x014E CAN0RXERR 00576 //0x014F CAN0TXERR 00577 //0x0150 – 0x0153 : CAN0IDAR0 – CAN0IDAR3 00578 //0x0154 – 0x0157 : CAN0IDMR0 – CAN0IDMR3 00579 //0x0158 – 0x015B : CAN0IDAR4 – CAN0IDAR7 00580 //0x015C – 0x015F : CAN0IDMR4 – CAN0IDMR7 00581 //0x0160 – 0x016F : CAN0RXFG 00582 //0x0170 – 0x017F : CAN0TXFG 00583 00584 00585 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& 00586 //this block applies to all can maps!!! 00587 // 00588 //0xXXX0 00589 //Extended ID 00590 //Standard ID 00591 //CANxRIDR0 00592 //0xXXX1 00593 //Extended ID 00594 //Standard ID 00595 //CANxRIDR1 00596 //0xXXX2 00597 //Extended ID 00598 //Standard ID 00599 //CANxRIDR2 00600 //0xXXX3 00601 //Extended ID 00602 //Standard ID 00603 //CANxRIDR3 00604 // 00605 //0xXXX4– 00606 //0xXXXB 00607 //CANxRDSR0– 00608 //CANxRDSR7 00609 //0xXXXC CANRxDLR 00610 //0xXXXD Reserved 00611 //0xXXXE CANxRTSRH 00612 //0xXXXF CANxRTSRL 00613 //0xXX10 00614 //Extended ID 00615 //CANxTIDR0 00616 //Standard ID 00617 // 00618 //0xXX0x 00619 //XX10 00620 //Extended ID 00621 //CANxTIDR1 00622 //Standard ID 00623 //0xXX12 00624 //Extended ID 00625 //CANxTIDR2 00626 //Standard ID 00627 //0xXX13 00628 //Extended ID 00629 //CANxTIDR3 00630 //Standard ID 00631 // 00632 //0xXX14– 00633 //0xXX1B 00634 //CANxTDSR0– 00635 //CANxTDSR7 00636 // 00637 //0xXX1C CANxTDLR 00638 //0xXX1D CANxTTBPR 00639 //0xXX1E CANxTTSRH 00640 //0xXX1F CANxTTSRL 00641 00642 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&77 00643 00644 00645 /* CAN1 don't want this for now, leave it disabled too. CAN1CTL1 bit 7 should be set to zero to disable this. */ 00646 //0x0180 CAN1CTL0 00647 #define CAN1CTL1 DVUCP(0x0181) 00648 //0x0182 CAN1BTR0 00649 //0x0183 CAN1BTR1 00650 //0x0184 CAN1RFLG 00651 //0x0185 CAN1RIER 00652 //0x0186 CAN1TFLG 00653 //0x0187 CAN1TIER 00654 //0x0188 CAN1TARQ 00655 //0x0189 CAN1TAAK 00656 //0x018A CAN1TBSEL 00657 //0x018B CAN1IDAC 00658 //0x018D CAN1MISC 00659 //0x018E CAN1RXERR 00660 //0x018F CAN1TXERR 00661 //0x0190 CAN1IDAR0 00662 //0x0191 CAN1IDAR1 00663 //0x0192 CAN1IDAR2 00664 //0x0193 CAN1IDAR3 00665 //0x0194 CAN1IDMR0 00666 //0x0195 CAN1IDMR1 00667 //0x0196 CAN1IDMR2 00668 //0x0197 CAN1IDMR3 00669 //0x0198 CAN1IDAR4 00670 //0x0199 CAN1IDAR5 00671 //0x019A CAN1IDAR6 00672 //0x019B CAN1IDAR7 00673 //0x019C CAN1IDMR4 00674 //0x019D CAN1IDMR5 00675 //0x019E CAN1IDMR6 00676 //0x019F CAN1IDMR7 00677 //0x01A0 – 0x01AF : CAN1RXFG 00678 //0x01B0 – 0x01BF : CAN1TXFG 00679 00680 00681 /* CAN2 CAN2CTL1 bit 7 should be set to zero to disable this. */ 00682 //0x01C0 CAN2CTL0 00683 //0x01C1 CAN2CTL1 00684 //0x01C2 CAN2BTR0 00685 //0x01C3 CAN2BTR1 00686 //0x01C4 CAN2RFLG 00687 //0x01C5 CAN2RIER 00688 //0x01C6 CAN2TFLG 00689 //0x01C7 CAN2TIER 00690 //0x01C8 CAN2TARQ 00691 //0x01C9 CAN2TAAK 00692 //0x01CA CAN2TBSEL 00693 //0x01CB CAN2IDAC 00694 //0x01CD CAN2MISC 00695 //0x01CE CAN2RXERR 00696 //0x01CF CAN2TXERR 00697 //0x01D0 CAN2IDAR0 00698 //0x01D1 CAN2IDAR1 00699 //0x01D2 CAN2IDAR2 00700 //0x01D3 CAN2IDAR3 00701 //0x01D4 CAN2IDMR0 00702 //0x01D5 CAN2IDMR1 00703 //0x01D6 CAN2IDMR2 00704 //0x01D7 CAN2IDMR3 00705 //0x01D8 CAN2IDAR4 00706 //0x01D9 CAN2IDAR5 00707 //0x01DA CAN2IDAR6 00708 //0x01DB CAN2IDAR7 00709 //0x01DC CAN2IDMR4 00710 //0x01DD CAN2IDMR5 00711 //0x01DE CAN2IDMR6 00712 //0x01DF CAN2IDMR7 00713 //0x01E0 – 0x01EF : CAN2RXFG 00714 //0x01F0 – 0x01FF : CAN2TXFG 00715 00716 00717 /* CAN3 CAN3CTL1 bit 7 should be set to zero to disable this. */ 00718 //0x0200 CAN3CTL0 00719 #define CAN3CTL1 DVUCP(0x0201) 00720 //0x0202 CAN3BTR0 00721 //0x0203 CAN3BTR1 00722 //0x0204 CAN3RFLG 00723 //0x0205 CAN3RIER 00724 //0x0206 CAN3TFLG 00725 //0x0207 CAN3TIER 00726 //0x0208 CAN3TARQ 00727 //0x0209 CAN3TAAK 00728 //0x020A CAN3TBSEL 00729 //0x020B CAN3IDAC 00730 //0x020E CAN3RXERR 00731 //0x020F CAN3TXERR 00732 //0x0210 CAN3IDAR0 00733 //0x0211 CAN3IDAR1 00734 //0x0212 CAN3IDAR2 00735 //0x0213 CAN3IDAR3 00736 //0x0214 CAN3IDMR0 00737 //0x0215 CAN3IDMR1 00738 //0x0216 CAN3IDMR2 00739 //0x0217 CAN3IDMR3 00740 //0x0218 CAN3IDAR4 00741 //0x0219 CAN3IDAR5 00742 //0x021A CAN3IDAR6 00743 //0x021B CAN3IDAR7 00744 //0x021C CAN3IDMR4 00745 //0x021D CAN3IDMR5 00746 //0x021E CAN3IDMR6 00747 //0x021F CAN3IDMR7 00748 //0x0220 – 0x022F : CAN3RXFG 00749 //0x0230 – 0x023F : CAN3TXFG 00750 00751 00752 /* CAN4 CAN4CTL1 bit 7 should be set to zero to disable this. */ 00753 //0x0280 CAN4CTL0 00754 #define CAN4CTL1 DVUCP(0x0281) 00755 //0x0282 CAN4BTR0 00756 //0x0283 CAN4BTR1 00757 //0x0284 CAN4RFLG 00758 //0x0285 CAN4RIER 00759 //0x0286 CAN4TFLG 00760 //0x0287 CAN4TIER 00761 //0x0288 CAN4TARQ 00762 //0x0289 CAN4TAAK 00763 //0x028A CAN4TBSEL 00764 //0x028B CAN4IDAC 00765 //0x028D CAN4MISC 00766 //0x028E CAN4RXERR 00767 //0x028F CAN4TXERR 00768 //0x0290 CAN4IDAR0 00769 //0x0291 CAN4IDAR1 00770 //0x0292 CAN4IDAR2 00771 //0x0293 CAN4IDAR3 00772 //0x0294 CAN4IDMR0 00773 //0x0295 CAN4IDMR1 00774 //0x0296 CAN4IDMR2 00775 //0x0297 CAN4IDMR3 00776 //0x0298 CAN4IDAR4 00777 //0x0299 CAN4IDAR5 00778 //0x029A CAN4IDAR6 00779 //0x029B CAN4IDAR7 00780 //0x029C CAN4IDMR4 00781 //0x029D CAN4IDMR5 00782 //0x029E CAN4IDMR6 00783 //0x029F CAN4IDMR7 00784 //0x02A0 – 0x02AF : CAN4RXFG 00785 //0x02B0 – 0x02BF : CAN4TXFG 00786 00787 00788 /* ATD0 TODO configure this as ATD inputs and try them out to control rate of flashing of leds etc, or even, which LED's are flashing etc */ 00789 #define ATD0CTL0 DVUCP(0x02C0) /* 0 - 2 define which ADC channel to wrap on when doing multiple channels */ 00790 #define ATD0CTL1 DVUCP(0x02C1) /* External trigger select when enabled in other control register */ 00791 #define ATD0CTL2 DVUCP(0x02C2) /* bit 7 turns the ADC block on. */ 00792 #define ATD0CTL3 DVUCP(0x02C3) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */ 00793 #define ATD0CTL4 DVUCP(0x02C4) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */ 00794 #define ATD0CTL5 DVUCP(0x02C5) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */ 00795 //0x02C6 ATD0STAT0 00796 //0x02CB ATD0STAT1 00797 #define ATD0DIEN DVUCP(0x02CD) /* Digital input enable */ 00798 //0x02CF ATD0PTAD0 digital use only 00799 #define ATD0_BASE 0x02D0 /* Maybe use this with a loop to sample them in a compact way. */ 00800 #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ /* IAT/MAT on my JimStim setup */ 00801 #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ /* CHT/CLT on my JimStim setup */ 00802 #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ /* TPS/TPS on my JimStim setup */ 00803 #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ /* EGO/O2 on my JimStim setup */ 00804 #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ /* BRV left of 3 one end of my h1 board */ 00805 #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ /* MAP mid of 3 one end of my h1 board */ 00806 #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ /* AAP right of 3 one end of my h1 board */ 00807 #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ /* SpareADC/SPARE on my JimStim setup */ 00808 00809 00810 /* VREG unit, Low Voltage Interrupt and Autonomous Periodical Interrupt */ 00811 #define VREGCTRL DVUCP(0x02F1) /* VReg Control Register */ 00812 #define VREGAPICL DVUCP(0x02F2) /* Autonomous Periodical Interrupt Control Register */ 00813 #define VREGAPITR DVUCP(0x02F3) /* Autonomous Periodical Interrupt Trimming Register */ 00814 #define VREGAPIR DVUSP(0x02F4) /* Autonomous Periodical Interrupt Rate High and Low Registers (VREGAPIRH DVUCP(0x02F4), VREGAPIRL DVUCP(0x02F5)) */ 00815 00816 00817 #define PWME DVUCP(0x0300) /* PWM enable register */ 00818 #define PWMPOL DVUCP(0x0301) /* PWM polarity register */ 00819 #define PWMCLK DVUCP(0x0302) /* PWM clock choice register */ 00820 #define PWMPRCLK DVUCP(0x0303) /* PWM Clock prescalers (bits 0,1,2 and bits 4,5,6 control 4 pins each) */ 00821 #define PWMCAE DVUCP(0x0304) /* PWM Center Align Enable Register */ 00822 #define PWMCTL DVUCP(0x0305) /* PWM Concatenate, stop, wait, freeze register */ 00823 #define PWMSCLA DVUCP(0x0308) /* PWM Scale A register */ 00824 #define PWMSCLB DVUCP(0x0309) /* PWM Scale B register */ 00825 #define PWMCNT0 DVUCP(0x030C) /* PWM 8 bit counter */ 00826 #define PWMCNT1 DVUCP(0x030D) /* */ 00827 #define PWMCNT2 DVUCP(0x030E) /* */ 00828 #define PWMCNT3 DVUCP(0x030F) /* */ 00829 #define PWMCNT4 DVUCP(0x0310) /* */ 00830 #define PWMCNT5 DVUCP(0x0311) /* */ 00831 #define PWMCNT6 DVUCP(0x0312) /* */ 00832 #define PWMCNT7 DVUCP(0x0313) /* PWM 8 bit counter */ 00833 #define PWMPER0 DVUCP(0x0314) /* PWM period value */ /* Ign LED 6 on my JimStim */ 00834 #define PWMPER1 DVUCP(0x0315) /* */ /* Ign LED 4 on my JimStim */ 00835 #define PWMPER2 DVUCP(0x0316) /* */ /* Ign LED 2 on my JimStim */ 00836 #define PWMPER3 DVUCP(0x0317) /* */ /* Ign LED 1 on my JimStim */ 00837 #define PWMPER4 DVUCP(0x0318) /* */ /* Ign LED 3 on my JimStim */ 00838 #define PWMPER5 DVUCP(0x0319) /* */ /* Ign LED 5 on my JimStim */ 00839 #define PWMPER6 DVUCP(0x031A) /* */ /* NC yet */ 00840 #define PWMPER7 DVUCP(0x031B) /* PWM period value */ /* NC yet */ 00841 #define PWMDTY0 DVUCP(0x031C) /* PWM duty cycle value */ 00842 #define PWMDTY1 DVUCP(0x031D) /* */ 00843 #define PWMDTY2 DVUCP(0x031E) /* */ 00844 #define PWMDTY3 DVUCP(0x031F) /* */ 00845 #define PWMDTY4 DVUCP(0x0320) /* */ 00846 #define PWMDTY5 DVUCP(0x0321) /* */ 00847 #define PWMDTY6 DVUCP(0x0322) /* */ 00848 #define PWMDTY7 DVUCP(0x0323) /* PWM duty cycle value */ 00849 #define PWMSDN DVUCP(0x0324) /* PWM shutdown behaviour register */ 00850 00851 00852 /* Periodic Interupt Timer with down counter */ 00853 #define PITCFLMT DVUCP(0x0340) /* PIT Control and Force Load Micro Timer Register, high bit enables, low 2 bits force load micro timers */ 00854 #define PITFLT DVUCP(0x0341) /* PIT Force Load Timer Register, low 4 bits force load timers */ 00855 #define PITCE DVUCP(0x0342) /* PIT Channel Enable Register, low 4 bits let the channel count */ 00856 #define PITMUX DVUCP(0x0343) /* PIT Multiplex Register, low 4 bits set which micro time base is used */ 00857 #define PITINTE DVUCP(0x0344) /* PIT Interrupt Enable Register, low four bits control the ISRs */ 00858 #define PITTF DVUCP(0x0345) /* PIT Time-Out Flag Register, low 4 bits set when each counter reaches 0 */ 00859 #define PITMTLD0 DVUCP(0x0346) /* PIT Micro Timer Load Register 0, time to start counting from when reaching zero */ 00860 #define PITMTLD1 DVUCP(0x0347) /* PIT Micro Timer Load Register 1, time to start counting from when reaching zero */ 00861 #define PITLD0 DVUSP(0x0348) /* PIT Load Register 0, time to start counting from when reaching zero (0x0348 PITLD0 (hi), 0x0349 PITLD0 (lo)) */ 00862 #define PITLD1 DVUSP(0x034C) /* PIT Load Register 1, time to start counting from when reaching zero (0x034C PITLD1 (hi), 0x034D PITLD1 (lo)) */ 00863 #define PITLD2 DVUSP(0x0350) /* PIT Load Register 2, time to start counting from when reaching zero (0x0350 PITLD2 (hi), 0x0351 PITLD2 (lo)) */ 00864 #define PITLD3 DVUSP(0x0354) /* PIT Load Register 3, time to start counting from when reaching zero (0x0354 PITLD3 (hi), 0x0355 PITLD3 (lo)) */ 00865 #define PITCNT0 DVUSP(0x034A) /* PIT Count Register 0, current value of down counter (0x034A PITCNT0 (hi), 0x034B PITCNT0 (lo)) */ 00866 #define PITCNT1 DVUSP(0x034E) /* PIT Count Register 1, current value of down counter (0x034E PITCNT1 (hi), 0x034F PITCNT1 (lo)) */ 00867 #define PITCNT2 DVUSP(0x0352) /* PIT Count Register 2, current value of down counter (0x0352 PITCNT2 (hi), 0x0353 PITCNT2 (lo)) */ 00868 #define PITCNT3 DVUSP(0x0356) /* PIT Count Register 3, current value of down counter (0x0356 PITCNT3 (hi), 0x0357 PITCNT3 (lo)) */ 00869 00870 00871 // TODO XGATE Set up stuff 00872 #define XGMCTL DVUSP(0x0380) /* TODO: 7th bit of this should be set to 0 for now to turn the XGATE off */ 00873 #define XGMCTLHI DVUCP(0x0380) 00874 #define XGMCTLLO DVUCP(0x0381) /* TODO: or 7th bit of this should be set to 0 for now to turn the XGATE off */ 00875 #define XGCHID DVUCP(0x0382) 00876 // unused on xdp512 #define XGVBR DVUCP(0x0384) 00877 // unused on xdp512 #define XGVBR DVUCP(0x0385) 00878 #define XGVBR DVUSP(0x0386) /* This is all that is used on the xdp512! 16 bit (0x0386 DVUCP (hi), 0x0387 DVUCP (lo)) */ 00879 #define XGIF_0 DVUCP(0x0388) 00880 #define XGIF_1 DVUCP(0x0389) 00881 #define XGIF_2 DVUCP(0x038A) 00882 #define XGIF_3 DVUCP(0x038B) /* WRONG value 0x023B stated in the manual as being both xgate and can3!!!!! should be 0x038B i believe!!!!! */ 00883 #define XGIF_4 DVUCP(0x038C) /* WRONG value 0x023C stated in the manual as being both xgate and can3!!!!! should be 0x038C i believe!!!!! */ 00884 #define XGIF_5 DVUCP(0x038D) 00885 #define XGIF_6 DVUCP(0x038E) 00886 #define XGIF_7 DVUCP(0x038F) 00887 #define XGIF_8 DVUCP(0x0390) 00888 #define XGIF_9 DVUCP(0x0391) 00889 #define XGIF_A DVUCP(0x0392) 00890 #define XGIF_B DVUCP(0x0393) 00891 #define XGIF_C DVUCP(0x0394) 00892 #define XGIF_D DVUCP(0x0395) 00893 #define XGIF_E DVUCP(0x0396) 00894 #define XGIF_F DVUCP(0x0397) 00895 #define XGSWT DVUSP(0x0398) 00896 //#define DVUCP(0x0399 XGSWT (lo) 00897 #define XGSEM DVUSP(0x039A) 00898 //#define DVUCP(0x039B XGSEM (lo) 00899 #define XGCCR DVUCP(0x039D) 00900 #define XGPC DVUSP(0x039E) 00901 //#define DVUCP(0x039F XGPC (lo) 00902 #define XGR1 DVUSP(0x03A2) 00903 //#define DVUCP(0x03A3 XGR1 (lo) 00904 #define XGR2 DVUSP(0x03A4) 00905 //#define DVUCP(0x03A5 XGR2 (lo) 00906 #define XGR3 DVUSP(0x03A6) 00907 //#define DVUCP(0x03A7 XGR3 (lo) 00908 #define XGR4 DVUSP(0x03A8) 00909 //#define DVUCP(0x03A9 XGR4 (lo) 00910 #define XGR5 DVUSP(0x03AA) 00911 //#define DVUCP(0x03AB XGR5 (lo) 00912 #define XGR6 DVUSP(0x03AC) 00913 //#define DVUCP(0x03AD XGR6 (lo) 00914 #define XGR7 DVUSP(0x03AE) 00915 //#define DVUCP(0x03AF XGR7 (lo) 00916 00917 00919 //0x0020 DBGC1 DVUCP() /* 00920 //0x0021 DBGSR DVUCP() /* 00921 //0x0022 DBGTCR DVUCP() /* 00922 //0x0023 DBGC2 DVUCP() /* 00923 //0x0024 DBGTBH DVUCP() /* 00924 //0x0025 DBGTBL DVUCP() /* 00925 //0x0026 DBGCNT DVUCP() /* 00926 //0x0027 DBGSCRX DVUCP() /* 00927 //COMPA 0x0028 DVUCP() /* 00928 //COMPC 0x0028 DVUCP() /* 00929 //DBGXCTL 0x0028 DVUCP() /* 00930 //COMPB 0x0028 DVUCP() /* 00931 //COMPD 0x0028 DVUCP() /* 00932 //0x0029 DBGXAH DVUCP() /* 00933 //0x002A DBGXAM DVUCP() /* 00934 //0x002B DBGXAL DVUCP() /* 00935 //0x002C DBGXDH DVUCP() /* 00936 //0x002D DBGXDL DVUCP() /* 00937 //0x002E DBGXDHM DVUCP() /* 00938 //0x002F DBGXDLM DVUCP() /* 00939 00940 00941 /* All reserved registers/blocks are listed here for reference */ 00942 00943 /* 0x003E CTCTL COP test register */ 00944 /* 0x006D TIMTST Timer test register */ 00945 /* 0x0102 FTSTMOD Flash test register */ 00946 /* 0x02C8 ATD0TEST0 ADC test register */ 00947 /* 0x02C9 ATD0TEST1 ADC test register */ 00948 /* 0x02F0 VREGHTCL VReg test register */ 00949 /* 0x0306 PWMTST PWM test register */ 00950 /* 0x0307 PWMPRSC PWM test register 2 */ 00951 /* 0x030A PWMSCNTA PWM test register 3 */ 00952 /* 0x030B PWMSCNTB PWM test register 4 */ 00953 00954 00955 /* 0x001D Reserved */ 00956 /* 0x001F Reserved */ 00957 /* 0x0012 Reserved */ 00958 /* 0x0014 - 0x0015 : Reserved */ 00959 /* 0x0018 - 0x0019 : Reserved */ 00960 /* 0x0031 Reserved */ 00961 /* 0x006C Reserved */ 00962 /* 0x00B5 - 0x00B7 : Reserved */ 00963 /* 0x0087 Reserved */ 00964 /* 0x00DC Reserved */ 00965 /* 0x00DE - 0x00DF : Reserved */ 00966 /* 0x00E5 - 0x00EF : Reserved */ 00967 /* 0x00F4 Reserved */ 00968 /* 0x00F6 Reserved */ 00969 /* 0x00F7 Reserved */ 00970 /* 0x00FC Reserved */ 00971 /* 0x00FE - 0x00FF : Reserved */ 00972 /* 0x010C - 0x010F : Reserved */ 00973 /* 0x0111 Reserved */ 00974 /* 0x0112 Reserved */ 00975 /* 0x0117 Reserved */ 00976 /* 0x0120 Reserved */ 00977 /* 0x0122 - 0x0125 : Reserved */ 00978 /* 0x014C Reserved */ 00979 /* 0x018C Reserved */ 00980 /* 0x01CC Reserved */ 00981 /* 0x020C - 0x020D : Reserved */ 00982 /* 0x0246 - 0x0247 : Reserved */ 00983 /* 0x024F Reserved */ 00984 /* 0x0270 Reserved */ 00985 /* 0x0272 Reserved */ 00986 /* 0x0274 Reserved */ 00987 /* 0x0276 Reserved */ 00988 /* 0x028C Reserved */ 00989 /* 0x02C7 Reserved */ 00990 /* 0x02CA Reserved */ 00991 /* 0x02CC Reserved */ 00992 /* 0x02CE Reserved */ 00993 /* 0x02E0 – 0x02EF : Reserved */ 00994 /* 0x02F6 – 0x02FF : Reserved */ 00995 /* 0x0325 – 0x033F : Reserved */ 00996 /* 0x0358 – 0x037F : Reserved */ 00997 /* 0x0383 Reserved */ 00998 /* 0x039C Reserved */ 00999 /* 0x03A0 Reserved */ 01000 /* 0x03A1 Reserved */ 01001 /* 0x03B0 – 0x07FF : Reserved */ 01002 01003 01004 /* Clear any accidental use of Reserved from typing mistakes. */ 01005 #ifdef Reserved 01006 #error "We have accidentally defined reserved as Reserved in here, find it and fix it." 01007 #endif 01008 01009 01010 #else 01011 /* let us know if we are being untidy with headers */ 01012 #warning "Header file 9S12XDP512_H seen before, sort it out!" 01013 /* end of the wrapper ifdef from the very top */ 01014 #endif
1.6.3