9S12XDP512.h File Reference
MC9S12XDP512 register definitions. More...
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Defines | |
| #define | DVUCP(address) (*((volatile unsigned char*)(address))) |
| #define | DVUSP(address) (*((volatile unsigned short*)(address))) |
| #define | AVUCP(address) ((volatile unsigned char*)(address)) |
| #define | AVUSP(address) ((volatile unsigned short*)(address)) |
| #define | PORTS_BA DVUSP(0x0001) |
| #define | PORTA DVUCP(0x0000) |
| #define | PORTB DVUCP(0x0001) |
| #define | PORTE DVUCP(0x0008) |
| #define | PORTK DVUCP(0x0032) |
| #define | DDRA DVUCP(0x0002) |
| #define | DDRB DVUCP(0x0003) |
| #define | DDRE DVUCP(0x0009) |
| #define | DDRK DVUCP(0x0033) |
| #define | DDRC DVUCP(0x0006) |
| #define | DDRD DVUCP(0x0007) |
| #define | PUCR DVUCP(0x000C) |
| #define | RDRIV DVUCP(0x000D) |
| #define | ECLKCTL DVUCP(0x001C) |
| #define | IRQCR DVUCP(0x001E) |
| #define | PTT DVUCP(0x0240) |
| #define | PORTT DVUCP(0x0240) |
| #define | PTIT DVUCP(0x0241) |
| #define | DDRT DVUCP(0x0242) |
| #define | RDRT DVUCP(0x0243) |
| #define | PERT DVUCP(0x0244) |
| #define | PPST DVUCP(0x0245) |
| #define | PTS DVUCP(0x0248) |
| #define | PORTS DVUCP(0x0248) |
| #define | PTIS DVUCP(0x0249) |
| #define | DDRS DVUCP(0x024A) |
| #define | RDRS DVUCP(0x024B) |
| #define | PERS DVUCP(0x024C) |
| #define | PPSS DVUCP(0x024D) |
| #define | WOMS DVUCP(0x024E) |
| #define | PTM DVUCP(0x0250) |
| #define | PORTM DVUCP(0x0250) |
| #define | PTIM DVUCP(0x0251) |
| #define | DDRM DVUCP(0x0252) |
| #define | RDRM DVUCP(0x0253) |
| #define | PERM DVUCP(0x0254) |
| #define | PPSM DVUCP(0x0255) |
| #define | WOMM DVUCP(0x0256) |
| #define | MODRR DVUCP(0x0257) |
| #define | PTP DVUCP(0x0258) |
| #define | PORTP DVUCP(0x0258) |
| #define | PTIP DVUCP(0x0259) |
| #define | DDRP DVUCP(0x025A) |
| #define | RDRP DVUCP(0x025B) |
| #define | PERP DVUCP(0x025C) |
| #define | PPSP DVUCP(0x025D) |
| #define | PIEP DVUCP(0x025E) |
| #define | PIFP DVUCP(0x025F) |
| #define | PTH DVUCP(0x0260) |
| #define | PORTH DVUCP(0x0260) |
| #define | PTIH DVUCP(0x0261) |
| #define | DDRH DVUCP(0x0262) |
| #define | RDRH DVUCP(0x0263) |
| #define | PERH DVUCP(0x0264) |
| #define | PPSH DVUCP(0x0265) |
| #define | PIEH DVUCP(0x0266) |
| #define | PIFH DVUCP(0x0267) |
| #define | PTJ DVUCP(0x0268) |
| #define | PORTJ DVUCP(0x0268) |
| #define | PTIJ DVUCP(0x0269) |
| #define | DDRJ DVUCP(0x026A) |
| #define | RDRJ DVUCP(0x026B) |
| #define | PERJ DVUCP(0x026C) |
| #define | PPSJ DVUCP(0x026D) |
| #define | PIEJ DVUCP(0x026E) |
| #define | PIFJ DVUCP(0x026F) |
| #define | ATD0PER1 DVUCP(0x0277) |
| #define | RPAGE DVUCP(0x0016) |
| #define | PPAGE DVUCP(0x0030) |
| #define | SYNR DVUCP(0x0034) |
| #define | REFDV DVUCP(0x0035) |
| #define | CRGFLG DVUCP(0x0037) |
| #define | CRGINT DVUCP(0x0038) |
| #define | CLKSEL DVUCP(0x0039) |
| #define | PLLCTL DVUCP(0x003A) |
| #define | RTICTL DVUCP(0x003B) |
| #define | COPCTL DVUCP(0x003C) |
| #define | ARMCOP DVUCP(0x003F) |
| #define | TCNT DVUSP(0x0044) |
| #define | TIOS DVUCP(0x0040) |
| #define | TIE DVUCP(0x004C) |
| #define | TSCR1 DVUCP(0x0046) |
| #define | TSCR2 DVUCP(0x004D) |
| #define | TFLG DVUCP(0x004E) |
| #define | TFLGOF DVUCP(0x004F) |
| #define | PTPSR DVUCP(0x006E) |
| #define | TTOV DVUCP(0x0047) |
| #define | CFORC DVUCP(0x0041) |
| #define | OC7M DVUCP(0x0042) |
| #define | OC7D DVUCP(0x0043) |
| #define | TCTL1 DVUCP(0x0048) |
| #define | TCTL2 DVUCP(0x0049) |
| #define | TCTL1_ADDR AVUCP(0x0048) |
| #define | TCTL2_ADDR AVUCP(0x0049) |
| #define | DLYCT DVUCP(0x0069) |
| #define | ICSYS DVUCP(0x006B) |
| #define | ICOVW DVUCP(0x006A) |
| #define | TCTL3 DVUCP(0x004A) |
| #define | TCTL4 DVUCP(0x004B) |
| #define | TC0H DVUSP(0x0078) |
| #define | TC1H DVUSP(0x007A) |
| #define | TC2H DVUSP(0x007C) |
| #define | TC3H DVUSP(0x007E) |
| #define | TC0 DVUSP(0x0050) |
| #define | TC1 DVUSP(0x0052) |
| #define | TC2 DVUSP(0x0054) |
| #define | TC3 DVUSP(0x0056) |
| #define | TC4 DVUSP(0x0058) |
| #define | TC5 DVUSP(0x005A) |
| #define | TC6 DVUSP(0x005C) |
| #define | TC7 DVUSP(0x005E) |
| #define | TC2_ADDR AVUSP(0x0054) |
| #define | TC3_ADDR AVUSP(0x0056) |
| #define | TC4_ADDR AVUSP(0x0058) |
| #define | TC5_ADDR AVUSP(0x005A) |
| #define | TC6_ADDR AVUSP(0x005C) |
| #define | TC7_ADDR AVUSP(0x005E) |
| #define | ICPAR DVUCP(0x0068) |
| #define | PACTL DVUCP(0x0060) |
| #define | PAFLG DVUCP(0x0061) |
| #define | PBCTL DVUCP(0x0070) |
| #define | PBFLG DVUCP(0x0071) |
| #define | PACNUS2 DVUSP(0x0062) |
| #define | PACNUS0 DVUSP(0x0064) |
| #define | PACN3 DVUCP(0x0062) |
| #define | PACN2 DVUCP(0x0063) |
| #define | PACN1 DVUCP(0x0064) |
| #define | PACN0 DVUCP(0x0065) |
| #define | PACHUS2 DVUSP(0x0072) |
| #define | PACHUS0 DVUSP(0x0074) |
| #define | PA3H DVUCP(0x0072) |
| #define | PA2H DVUCP(0x0073) |
| #define | PA1H DVUCP(0x0074) |
| #define | PA0H DVUCP(0x0075) |
| #define | MCCTL DVUCP(0x0066) |
| #define | MCFLG DVUCP(0x0067) |
| #define | MCCNT DVUSP(0x0076) |
| #define | PTMCPSR DVUCP(0x006F) |
| #define | ATD1CTL0 DVUCP(0x0080) |
| #define | ATD1CTL1 DVUCP(0x0081) |
| #define | ATD1CTL2 DVUCP(0x0082) |
| #define | ATD1CTL3 DVUCP(0x0083) |
| #define | ATD1CTL4 DVUCP(0x0084) |
| #define | ATD1CTL5 DVUCP(0x0085) |
| #define | ATD1DIEN0 DVUCP(0x008C) |
| #define | ATD1DIEN1 DVUCP(0x008D) |
| #define | ATD1_BASE 0x0090 |
| #define | ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ |
| #define | ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ |
| #define | ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ |
| #define | ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ |
| #define | ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ |
| #define | ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ |
| #define | ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ |
| #define | ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ |
| #define | SCI0_BASE 0x00C8 |
| #define | SCI0BD DVUSP(SCI0_BASE + 0x0) |
| #define | SCI0CR1 DVUCP(SCI0_BASE + 0x2) |
| #define | SCI0ASR1 DVUCP(SCI0_BASE + 0x0) |
| #define | SCI0ACR1 DVUCP(SCI0_BASE + 0x1) |
| #define | SCI0ACR2 DVUCP(SCI0_BASE + 0x2) |
| #define | SCI0CR2 DVUCP(SCI0_BASE + 0x3) |
| #define | SCI0SR1 DVUCP(SCI0_BASE + 0x4) |
| #define | SCI0SR2 DVUCP(SCI0_BASE + 0x5) |
| #define | SCI0DRH DVUCP(SCI0_BASE + 0x6) |
| #define | SCI0DRL DVUCP(SCI0_BASE + 0x7) |
| #define | FCLKDIV DVUCP(0x0100) |
| #define | FSEC DVUCP(0x0101) |
| #define | FCNFG DVUCP(0x0103) |
| #define | FPROT DVUCP(0x0104) |
| #define | FSTAT DVUCP(0x0105) |
| #define | FCMD DVUCP(0x0106) |
| #define | FCTL DVUCP(0x0107) |
| #define | FADDR DVUSP(0x0108) |
| #define | FDATA DVUSP(0x010A) |
| #define | IVBR DVUCP(0x0121) |
| #define | INT_XGPRIO DVUCP(0x0126) |
| #define | INT_CFADDR DVUCP(0x0127) |
| #define | INT_CFDATA0 DVUCP(0x0128) |
| #define | INT_CFDATA1 DVUCP(0x0129) |
| #define | INT_CFDATA2 DVUCP(0x012A) |
| #define | INT_CFDATA3 DVUCP(0x012B) |
| #define | INT_CFDATA4 DVUCP(0x012C) |
| #define | INT_CFDATA5 DVUCP(0x012D) |
| #define | INT_CFDATA6 DVUCP(0x012E) |
| #define | INT_CFDATA7 DVUCP(0x012F) |
| #define | CAN0CTL1 DVUCP(0x0141) |
| #define | CAN1CTL1 DVUCP(0x0181) |
| #define | CAN3CTL1 DVUCP(0x0201) |
| #define | CAN4CTL1 DVUCP(0x0281) |
| #define | ATD0CTL0 DVUCP(0x02C0) |
| #define | ATD0CTL1 DVUCP(0x02C1) |
| #define | ATD0CTL2 DVUCP(0x02C2) |
| #define | ATD0CTL3 DVUCP(0x02C3) |
| #define | ATD0CTL4 DVUCP(0x02C4) |
| #define | ATD0CTL5 DVUCP(0x02C5) |
| #define | ATD0DIEN DVUCP(0x02CD) |
| #define | ATD0_BASE 0x02D0 |
| #define | ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ |
| #define | ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ |
| #define | ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ |
| #define | ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ |
| #define | ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ |
| #define | ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ |
| #define | ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ |
| #define | ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ |
| #define | VREGCTRL DVUCP(0x02F1) |
| #define | VREGAPICL DVUCP(0x02F2) |
| #define | VREGAPITR DVUCP(0x02F3) |
| #define | VREGAPIR DVUSP(0x02F4) |
| #define | PWME DVUCP(0x0300) |
| #define | PWMPOL DVUCP(0x0301) |
| #define | PWMCLK DVUCP(0x0302) |
| #define | PWMPRCLK DVUCP(0x0303) |
| #define | PWMCAE DVUCP(0x0304) |
| #define | PWMCTL DVUCP(0x0305) |
| #define | PWMSCLA DVUCP(0x0308) |
| #define | PWMSCLB DVUCP(0x0309) |
| #define | PWMCNT0 DVUCP(0x030C) |
| #define | PWMCNT1 DVUCP(0x030D) |
| #define | PWMCNT2 DVUCP(0x030E) |
| #define | PWMCNT3 DVUCP(0x030F) |
| #define | PWMCNT4 DVUCP(0x0310) |
| #define | PWMCNT5 DVUCP(0x0311) |
| #define | PWMCNT6 DVUCP(0x0312) |
| #define | PWMCNT7 DVUCP(0x0313) |
| #define | PWMPER0 DVUCP(0x0314) /* PWM period value */ |
| #define | PWMPER1 DVUCP(0x0315) /* */ |
| #define | PWMPER2 DVUCP(0x0316) /* */ |
| #define | PWMPER3 DVUCP(0x0317) /* */ |
| #define | PWMPER4 DVUCP(0x0318) /* */ |
| #define | PWMPER5 DVUCP(0x0319) /* */ |
| #define | PWMPER6 DVUCP(0x031A) /* */ |
| #define | PWMPER7 DVUCP(0x031B) /* PWM period value */ |
| #define | PWMDTY0 DVUCP(0x031C) |
| #define | PWMDTY1 DVUCP(0x031D) |
| #define | PWMDTY2 DVUCP(0x031E) |
| #define | PWMDTY3 DVUCP(0x031F) |
| #define | PWMDTY4 DVUCP(0x0320) |
| #define | PWMDTY5 DVUCP(0x0321) |
| #define | PWMDTY6 DVUCP(0x0322) |
| #define | PWMDTY7 DVUCP(0x0323) |
| #define | PWMSDN DVUCP(0x0324) |
| #define | PITCFLMT DVUCP(0x0340) |
| #define | PITFLT DVUCP(0x0341) |
| #define | PITCE DVUCP(0x0342) |
| #define | PITMUX DVUCP(0x0343) |
| #define | PITINTE DVUCP(0x0344) |
| #define | PITTF DVUCP(0x0345) |
| #define | PITMTLD0 DVUCP(0x0346) |
| #define | PITMTLD1 DVUCP(0x0347) |
| #define | PITLD0 DVUSP(0x0348) |
| #define | PITLD1 DVUSP(0x034C) |
| #define | PITLD2 DVUSP(0x0350) |
| #define | PITLD3 DVUSP(0x0354) |
| #define | PITCNT0 DVUSP(0x034A) |
| #define | PITCNT1 DVUSP(0x034E) |
| #define | PITCNT2 DVUSP(0x0352) |
| #define | PITCNT3 DVUSP(0x0356) |
| #define | XGMCTL DVUSP(0x0380) |
| #define | XGMCTLHI DVUCP(0x0380) |
| #define | XGMCTLLO DVUCP(0x0381) |
| #define | XGCHID DVUCP(0x0382) |
| #define | XGVBR DVUSP(0x0386) |
| #define | XGIF_0 DVUCP(0x0388) |
| #define | XGIF_1 DVUCP(0x0389) |
| #define | XGIF_2 DVUCP(0x038A) |
| #define | XGIF_3 DVUCP(0x038B) |
| #define | XGIF_4 DVUCP(0x038C) |
| #define | XGIF_5 DVUCP(0x038D) |
| #define | XGIF_6 DVUCP(0x038E) |
| #define | XGIF_7 DVUCP(0x038F) |
| #define | XGIF_8 DVUCP(0x0390) |
| #define | XGIF_9 DVUCP(0x0391) |
| #define | XGIF_A DVUCP(0x0392) |
| #define | XGIF_B DVUCP(0x0393) |
| #define | XGIF_C DVUCP(0x0394) |
| #define | XGIF_D DVUCP(0x0395) |
| #define | XGIF_E DVUCP(0x0396) |
| #define | XGIF_F DVUCP(0x0397) |
| #define | XGSWT DVUSP(0x0398) |
| #define | XGSEM DVUSP(0x039A) |
| #define | XGCCR DVUCP(0x039D) |
| #define | XGPC DVUSP(0x039E) |
| #define | XGR1 DVUSP(0x03A2) |
| #define | XGR2 DVUSP(0x03A4) |
| #define | XGR3 DVUSP(0x03A6) |
| #define | XGR4 DVUSP(0x03A8) |
| #define | XGR5 DVUSP(0x03AA) |
| #define | XGR6 DVUSP(0x03AC) |
| #define | XGR7 DVUSP(0x03AE) |
Detailed Description
MC9S12XDP512 register definitions.
This is the device header for the FreeScale MC9S12XDP512 MCU. It contains declarations that allow access to all of the devices control registers.
These are the full basic register definitions for the Freescale 9S12XDP512 processor as taken from MC9S12XDP512V2.pdf Appendix G
Definition in file 9S12XDP512.h.
Define Documentation
| #define ARMCOP DVUCP(0x003F) |
Definition at line 238 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond().
| #define ATD0_BASE 0x02D0 |
Definition at line 799 of file 9S12XDP512.h.
Referenced by sampleLoopADC().
| #define ATD0CTL0 DVUCP(0x02C0) |
Definition at line 789 of file 9S12XDP512.h.
| #define ATD0CTL1 DVUCP(0x02C1) |
Definition at line 790 of file 9S12XDP512.h.
| #define ATD0CTL2 DVUCP(0x02C2) |
Definition at line 791 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD0CTL3 DVUCP(0x02C3) |
Definition at line 792 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD0CTL4 DVUCP(0x02C4) |
Definition at line 793 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD0CTL5 DVUCP(0x02C5) |
Definition at line 794 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD0DIEN DVUCP(0x02CD) |
Definition at line 797 of file 9S12XDP512.h.
| #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ |
Definition at line 800 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ |
Definition at line 801 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ |
Definition at line 802 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ |
Definition at line 803 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ |
Definition at line 804 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ |
Definition at line 805 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ |
Definition at line 806 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ |
Definition at line 807 of file 9S12XDP512.h.
Referenced by adjustPWM(), and sampleEachADC().
| #define ATD0PER1 DVUCP(0x0277) |
Definition at line 181 of file 9S12XDP512.h.
| #define ATD1_BASE 0x0090 |
Definition at line 362 of file 9S12XDP512.h.
Referenced by sampleLoopADC().
| #define ATD1CTL0 DVUCP(0x0080) |
Definition at line 346 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD1CTL1 DVUCP(0x0081) |
Definition at line 347 of file 9S12XDP512.h.
| #define ATD1CTL2 DVUCP(0x0082) |
Definition at line 348 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD1CTL3 DVUCP(0x0083) |
Definition at line 349 of file 9S12XDP512.h.
Referenced by initIO().
| #define ATD1CTL4 DVUCP(0x0084) |
Definition at line 350 of file 9S12XDP512.h.
| #define ATD1CTL5 DVUCP(0x0085) |
Definition at line 351 of file 9S12XDP512.h.
| #define ATD1DIEN0 DVUCP(0x008C) |
Definition at line 357 of file 9S12XDP512.h.
| #define ATD1DIEN1 DVUCP(0x008D) |
Definition at line 358 of file 9S12XDP512.h.
| #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ |
Definition at line 363 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ |
Definition at line 364 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ |
Definition at line 365 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ |
Definition at line 366 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ |
Definition at line 367 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ |
Definition at line 368 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ |
Definition at line 369 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ |
Definition at line 370 of file 9S12XDP512.h.
Referenced by sampleEachADC().
| #define AVUCP | ( | address | ) | ((volatile unsigned char*)(address)) |
Definition at line 59 of file 9S12XDP512.h.
| #define AVUSP | ( | address | ) | ((volatile unsigned short*)(address)) |
Definition at line 61 of file 9S12XDP512.h.
| #define CAN0CTL1 DVUCP(0x0141) |
Definition at line 563 of file 9S12XDP512.h.
| #define CAN1CTL1 DVUCP(0x0181) |
Definition at line 647 of file 9S12XDP512.h.
| #define CAN3CTL1 DVUCP(0x0201) |
Definition at line 719 of file 9S12XDP512.h.
| #define CAN4CTL1 DVUCP(0x0281) |
Definition at line 754 of file 9S12XDP512.h.
| #define CFORC DVUCP(0x0041) |
Definition at line 258 of file 9S12XDP512.h.
| #define CLKSEL DVUCP(0x0039) |
Definition at line 233 of file 9S12XDP512.h.
Referenced by initPLL().
| #define COPCTL DVUCP(0x003C) |
Definition at line 236 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond().
| #define CRGFLG DVUCP(0x0037) |
Definition at line 231 of file 9S12XDP512.h.
Referenced by initInterrupts(), initPLL(), and RTIISR().
| #define CRGINT DVUCP(0x0038) |
Definition at line 232 of file 9S12XDP512.h.
Referenced by initInterrupts().
| #define DDRA DVUCP(0x0002) |
Definition at line 79 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRB DVUCP(0x0003) |
Definition at line 80 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRC DVUCP(0x0006) |
Definition at line 85 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRD DVUCP(0x0007) |
Definition at line 86 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRE DVUCP(0x0009) |
Definition at line 81 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRH DVUCP(0x0262) |
Definition at line 158 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRJ DVUCP(0x026A) |
Definition at line 170 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRK DVUCP(0x0033) |
Definition at line 82 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRM DVUCP(0x0252) |
Definition at line 131 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRP DVUCP(0x025A) |
Definition at line 146 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRS DVUCP(0x024A) |
Definition at line 120 of file 9S12XDP512.h.
Referenced by initIO().
| #define DDRT DVUCP(0x0242) |
Definition at line 110 of file 9S12XDP512.h.
Referenced by initIO().
| #define DLYCT DVUCP(0x0069) |
Definition at line 275 of file 9S12XDP512.h.
| #define DVUCP | ( | address | ) | (*((volatile unsigned char*)(address))) |
Definition at line 54 of file 9S12XDP512.h.
| #define DVUSP | ( | address | ) | (*((volatile unsigned short*)(address))) |
Definition at line 56 of file 9S12XDP512.h.
Referenced by sampleLoopADC().
| #define ECLKCTL DVUCP(0x001C) |
Definition at line 102 of file 9S12XDP512.h.
| #define FADDR DVUSP(0x0108) |
Definition at line 503 of file 9S12XDP512.h.
| #define FCLKDIV DVUCP(0x0100) |
Definition at line 495 of file 9S12XDP512.h.
Referenced by initFlash().
| #define FCMD DVUCP(0x0106) |
Definition at line 500 of file 9S12XDP512.h.
Referenced by eraseSector(), and writeWord().
| #define FCNFG DVUCP(0x0103) |
Definition at line 497 of file 9S12XDP512.h.
| #define FCTL DVUCP(0x0107) |
Definition at line 501 of file 9S12XDP512.h.
| #define FDATA DVUSP(0x010A) |
Definition at line 504 of file 9S12XDP512.h.
| #define FPROT DVUCP(0x0104) |
Definition at line 498 of file 9S12XDP512.h.
Referenced by initFlash().
| #define FSEC DVUCP(0x0101) |
Definition at line 496 of file 9S12XDP512.h.
| #define FSTAT DVUCP(0x0105) |
Definition at line 499 of file 9S12XDP512.h.
Referenced by eraseSector(), initFlash(), and writeWord().
| #define ICOVW DVUCP(0x006A) |
Definition at line 277 of file 9S12XDP512.h.
| #define ICPAR DVUCP(0x0068) |
Definition at line 314 of file 9S12XDP512.h.
| #define ICSYS DVUCP(0x006B) |
Definition at line 276 of file 9S12XDP512.h.
| #define INT_CFADDR DVUCP(0x0127) |
Definition at line 522 of file 9S12XDP512.h.
Referenced by initXgate().
| #define INT_CFDATA0 DVUCP(0x0128) |
Definition at line 523 of file 9S12XDP512.h.
Referenced by initXgate().
| #define INT_CFDATA1 DVUCP(0x0129) |
Definition at line 524 of file 9S12XDP512.h.
Referenced by initXgate().
| #define INT_CFDATA2 DVUCP(0x012A) |
Definition at line 525 of file 9S12XDP512.h.
| #define INT_CFDATA3 DVUCP(0x012B) |
Definition at line 526 of file 9S12XDP512.h.
| #define INT_CFDATA4 DVUCP(0x012C) |
Definition at line 527 of file 9S12XDP512.h.
| #define INT_CFDATA5 DVUCP(0x012D) |
Definition at line 528 of file 9S12XDP512.h.
| #define INT_CFDATA6 DVUCP(0x012E) |
Definition at line 529 of file 9S12XDP512.h.
| #define INT_CFDATA7 DVUCP(0x012F) |
Definition at line 530 of file 9S12XDP512.h.
| #define INT_XGPRIO DVUCP(0x0126) |
Definition at line 521 of file 9S12XDP512.h.
| #define IRQCR DVUCP(0x001E) |
Definition at line 103 of file 9S12XDP512.h.
| #define IVBR DVUCP(0x0121) |
Definition at line 520 of file 9S12XDP512.h.
Referenced by initInterrupts().
| #define MCCNT DVUSP(0x0076) |
Definition at line 340 of file 9S12XDP512.h.
Referenced by initECTTimer(), and ModDownCtrISR().
| #define MCCTL DVUCP(0x0066) |
Definition at line 338 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define MCFLG DVUCP(0x0067) |
Definition at line 339 of file 9S12XDP512.h.
Referenced by initECTTimer(), and ModDownCtrISR().
| #define MODRR DVUCP(0x0257) |
Definition at line 139 of file 9S12XDP512.h.
| #define OC7D DVUCP(0x0043) |
Definition at line 260 of file 9S12XDP512.h.
| #define OC7M DVUCP(0x0042) |
Definition at line 259 of file 9S12XDP512.h.
| #define PA0H DVUCP(0x0075) |
Definition at line 334 of file 9S12XDP512.h.
| #define PA1H DVUCP(0x0074) |
Definition at line 333 of file 9S12XDP512.h.
| #define PA2H DVUCP(0x0073) |
Definition at line 332 of file 9S12XDP512.h.
| #define PA3H DVUCP(0x0072) |
Definition at line 331 of file 9S12XDP512.h.
| #define PACHUS0 DVUSP(0x0074) |
Definition at line 330 of file 9S12XDP512.h.
| #define PACHUS2 DVUSP(0x0072) |
Definition at line 329 of file 9S12XDP512.h.
| #define PACN0 DVUCP(0x0065) |
Definition at line 327 of file 9S12XDP512.h.
Referenced by changeSyncStatus().
| #define PACN1 DVUCP(0x0064) |
Definition at line 326 of file 9S12XDP512.h.
| #define PACN2 DVUCP(0x0063) |
Definition at line 325 of file 9S12XDP512.h.
| #define PACN3 DVUCP(0x0062) |
Definition at line 324 of file 9S12XDP512.h.
| #define PACNUS0 DVUSP(0x0064) |
Definition at line 323 of file 9S12XDP512.h.
| #define PACNUS2 DVUSP(0x0062) |
Definition at line 322 of file 9S12XDP512.h.
| #define PACTL DVUCP(0x0060) |
Definition at line 317 of file 9S12XDP512.h.
Referenced by changeSyncStatus().
| #define PAFLG DVUCP(0x0061) |
Definition at line 318 of file 9S12XDP512.h.
| #define PBCTL DVUCP(0x0070) |
Definition at line 319 of file 9S12XDP512.h.
| #define PBFLG DVUCP(0x0071) |
Definition at line 320 of file 9S12XDP512.h.
| #define PERH DVUCP(0x0264) |
Definition at line 160 of file 9S12XDP512.h.
| #define PERJ DVUCP(0x026C) |
Definition at line 172 of file 9S12XDP512.h.
| #define PERM DVUCP(0x0254) |
Definition at line 133 of file 9S12XDP512.h.
| #define PERP DVUCP(0x025C) |
Definition at line 148 of file 9S12XDP512.h.
| #define PERS DVUCP(0x024C) |
Definition at line 122 of file 9S12XDP512.h.
| #define PERT DVUCP(0x0244) |
Definition at line 112 of file 9S12XDP512.h.
| #define PIEH DVUCP(0x0266) |
Definition at line 162 of file 9S12XDP512.h.
Referenced by initInterrupts().
| #define PIEJ DVUCP(0x026E) |
Definition at line 174 of file 9S12XDP512.h.
| #define PIEP DVUCP(0x025E) |
Definition at line 150 of file 9S12XDP512.h.
| #define PIFH DVUCP(0x0267) |
Definition at line 163 of file 9S12XDP512.h.
Referenced by initInterrupts(), and PortHISR().
| #define PIFJ DVUCP(0x026F) |
Definition at line 175 of file 9S12XDP512.h.
Referenced by PortJISR().
| #define PIFP DVUCP(0x025F) |
Definition at line 151 of file 9S12XDP512.h.
Referenced by PortPISR().
| #define PITCE DVUCP(0x0342) |
Definition at line 855 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
| #define PITCFLMT DVUCP(0x0340) |
Definition at line 853 of file 9S12XDP512.h.
Referenced by initPITTimer().
| #define PITCNT0 DVUSP(0x034A) |
Definition at line 865 of file 9S12XDP512.h.
Referenced by PrimaryRPMISR().
| #define PITCNT1 DVUSP(0x034E) |
Definition at line 866 of file 9S12XDP512.h.
Referenced by PrimaryRPMISR().
| #define PITCNT2 DVUSP(0x0352) |
Definition at line 867 of file 9S12XDP512.h.
| #define PITCNT3 DVUSP(0x0356) |
Definition at line 868 of file 9S12XDP512.h.
| #define PITFLT DVUCP(0x0341) |
Definition at line 854 of file 9S12XDP512.h.
| #define PITINTE DVUCP(0x0344) |
Definition at line 857 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), PrimaryRPMISR(), StagedOffISR(), and StagedOnISR().
| #define PITLD0 DVUSP(0x0348) |
Definition at line 861 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
| #define PITLD1 DVUSP(0x034C) |
Definition at line 862 of file 9S12XDP512.h.
Referenced by PrimaryRPMISR().
| #define PITLD2 DVUSP(0x0350) |
Definition at line 863 of file 9S12XDP512.h.
| #define PITLD3 DVUSP(0x0354) |
Definition at line 864 of file 9S12XDP512.h.
| #define PITMTLD0 DVUCP(0x0346) |
Definition at line 859 of file 9S12XDP512.h.
Referenced by initPITTimer().
| #define PITMTLD1 DVUCP(0x0347) |
Definition at line 860 of file 9S12XDP512.h.
Referenced by initPITTimer().
| #define PITMUX DVUCP(0x0343) |
Definition at line 856 of file 9S12XDP512.h.
| #define PITTF DVUCP(0x0345) |
Definition at line 858 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and PrimaryRPMISR().
| #define PLLCTL DVUCP(0x003A) |
Definition at line 234 of file 9S12XDP512.h.
Referenced by initPLL().
| #define PORTA DVUCP(0x0000) |
Definition at line 70 of file 9S12XDP512.h.
Referenced by initIO(), ModDownCtrISR(), PortHISR(), and SCI0ISR().
| #define PORTB DVUCP(0x0001) |
Definition at line 71 of file 9S12XDP512.h.
| #define PORTE DVUCP(0x0008) |
Definition at line 72 of file 9S12XDP512.h.
Referenced by initIO().
| #define PORTH DVUCP(0x0260) |
Definition at line 156 of file 9S12XDP512.h.
Referenced by initIO().
| #define PORTJ DVUCP(0x0268) |
Definition at line 168 of file 9S12XDP512.h.
Referenced by initIO(), main(), PrimaryRPMISR(), and SecondaryRPMISR().
| #define PORTK DVUCP(0x0032) |
Definition at line 73 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), initIO(), and main().
| #define PORTM DVUCP(0x0250) |
Definition at line 129 of file 9S12XDP512.h.
Referenced by initIO(), and SecondaryRPMISR().
| #define PORTP DVUCP(0x0258) |
Definition at line 144 of file 9S12XDP512.h.
Referenced by initIO(), and PrimaryRPMISR().
| #define PORTS DVUCP(0x0248) |
Definition at line 118 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and initIO().
| #define PORTS_BA DVUSP(0x0001) |
Definition at line 69 of file 9S12XDP512.h.
Referenced by IgnitionDwellISR(), IgnitionFireISR(), and initConfiguration().
| #define PORTT DVUCP(0x0240) |
Definition at line 108 of file 9S12XDP512.h.
Referenced by initIO().
| #define PPAGE DVUCP(0x0030) |
Definition at line 205 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), eraseSector(), initXgate(), lookupBlockDetails(), writeBlock(), and writeSector().
| #define PPSH DVUCP(0x0265) |
Definition at line 161 of file 9S12XDP512.h.
Referenced by initInterrupts().
| #define PPSJ DVUCP(0x026D) |
Definition at line 173 of file 9S12XDP512.h.
| #define PPSM DVUCP(0x0255) |
Definition at line 134 of file 9S12XDP512.h.
| #define PPSP DVUCP(0x025D) |
Definition at line 149 of file 9S12XDP512.h.
| #define PPSS DVUCP(0x024D) |
Definition at line 123 of file 9S12XDP512.h.
| #define PPST DVUCP(0x0245) |
Definition at line 113 of file 9S12XDP512.h.
| #define PTH DVUCP(0x0260) |
Definition at line 155 of file 9S12XDP512.h.
| #define PTIH DVUCP(0x0261) |
Definition at line 157 of file 9S12XDP512.h.
| #define PTIJ DVUCP(0x0269) |
Definition at line 169 of file 9S12XDP512.h.
| #define PTIM DVUCP(0x0251) |
Definition at line 130 of file 9S12XDP512.h.
| #define PTIP DVUCP(0x0259) |
Definition at line 145 of file 9S12XDP512.h.
| #define PTIS DVUCP(0x0249) |
Definition at line 119 of file 9S12XDP512.h.
| #define PTIT DVUCP(0x0241) |
Definition at line 109 of file 9S12XDP512.h.
Referenced by InjectorXISR(), PrimaryRPMISR(), and SecondaryRPMISR().
| #define PTJ DVUCP(0x0268) |
Definition at line 167 of file 9S12XDP512.h.
| #define PTM DVUCP(0x0250) |
Definition at line 128 of file 9S12XDP512.h.
| #define PTMCPSR DVUCP(0x006F) |
Definition at line 341 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define PTP DVUCP(0x0258) |
Definition at line 143 of file 9S12XDP512.h.
| #define PTPSR DVUCP(0x006E) |
Definition at line 254 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define PTS DVUCP(0x0248) |
Definition at line 117 of file 9S12XDP512.h.
| #define PTT DVUCP(0x0240) |
Definition at line 107 of file 9S12XDP512.h.
| #define PUCR DVUCP(0x000C) |
Definition at line 93 of file 9S12XDP512.h.
| #define PWMCAE DVUCP(0x0304) |
Definition at line 821 of file 9S12XDP512.h.
| #define PWMCLK DVUCP(0x0302) |
Definition at line 819 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMCNT0 DVUCP(0x030C) |
Definition at line 825 of file 9S12XDP512.h.
| #define PWMCNT1 DVUCP(0x030D) |
Definition at line 826 of file 9S12XDP512.h.
| #define PWMCNT2 DVUCP(0x030E) |
Definition at line 827 of file 9S12XDP512.h.
| #define PWMCNT3 DVUCP(0x030F) |
Definition at line 828 of file 9S12XDP512.h.
| #define PWMCNT4 DVUCP(0x0310) |
Definition at line 829 of file 9S12XDP512.h.
| #define PWMCNT5 DVUCP(0x0311) |
Definition at line 830 of file 9S12XDP512.h.
| #define PWMCNT6 DVUCP(0x0312) |
Definition at line 831 of file 9S12XDP512.h.
| #define PWMCNT7 DVUCP(0x0313) |
Definition at line 832 of file 9S12XDP512.h.
| #define PWMCTL DVUCP(0x0305) |
Definition at line 822 of file 9S12XDP512.h.
| #define PWMDTY0 DVUCP(0x031C) |
Definition at line 841 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY1 DVUCP(0x031D) |
Definition at line 842 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY2 DVUCP(0x031E) |
Definition at line 843 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY3 DVUCP(0x031F) |
Definition at line 844 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY4 DVUCP(0x0320) |
Definition at line 845 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY5 DVUCP(0x0321) |
Definition at line 846 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY6 DVUCP(0x0322) |
Definition at line 847 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWMDTY7 DVUCP(0x0323) |
Definition at line 848 of file 9S12XDP512.h.
Referenced by adjustPWM(), and initIO().
| #define PWME DVUCP(0x0300) |
Definition at line 817 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER0 DVUCP(0x0314) /* PWM period value */ |
Definition at line 833 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER1 DVUCP(0x0315) /* */ |
Definition at line 834 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER2 DVUCP(0x0316) /* */ |
Definition at line 835 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER3 DVUCP(0x0317) /* */ |
Definition at line 836 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER4 DVUCP(0x0318) /* */ |
Definition at line 837 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER5 DVUCP(0x0319) /* */ |
Definition at line 838 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER6 DVUCP(0x031A) /* */ |
Definition at line 839 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPER7 DVUCP(0x031B) /* PWM period value */ |
Definition at line 840 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMPOL DVUCP(0x0301) |
Definition at line 818 of file 9S12XDP512.h.
| #define PWMPRCLK DVUCP(0x0303) |
Definition at line 820 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMSCLA DVUCP(0x0308) |
Definition at line 823 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMSCLB DVUCP(0x0309) |
Definition at line 824 of file 9S12XDP512.h.
Referenced by initIO().
| #define PWMSDN DVUCP(0x0324) |
Definition at line 849 of file 9S12XDP512.h.
| #define RDRH DVUCP(0x0263) |
Definition at line 159 of file 9S12XDP512.h.
| #define RDRIV DVUCP(0x000D) |
Definition at line 99 of file 9S12XDP512.h.
| #define RDRJ DVUCP(0x026B) |
Definition at line 171 of file 9S12XDP512.h.
| #define RDRM DVUCP(0x0253) |
Definition at line 132 of file 9S12XDP512.h.
| #define RDRP DVUCP(0x025B) |
Definition at line 147 of file 9S12XDP512.h.
| #define RDRS DVUCP(0x024B) |
Definition at line 121 of file 9S12XDP512.h.
| #define RDRT DVUCP(0x0243) |
Definition at line 111 of file 9S12XDP512.h.
| #define REFDV DVUCP(0x0035) |
Definition at line 229 of file 9S12XDP512.h.
Referenced by initPLL().
| #define RPAGE DVUCP(0x0016) |
Definition at line 203 of file 9S12XDP512.h.
Referenced by decodePacketAndRespond(), initPagedRAMFuel(), initPagedRAMTime(), initPagedRAMTune(), initXgate(), lookupPagedMainTableCellValue(), setPagedMainTableCellValue(), setPagedMainTableLoadValue(), setPagedMainTableRPMValue(), setPagedTwoDTableAxisValue(), setPagedTwoDTableCellValue(), setupPagedRAM(), writeBlock(), and writeSector().
| #define RTICTL DVUCP(0x003B) |
Definition at line 235 of file 9S12XDP512.h.
Referenced by initInterrupts().
| #define SCI0_BASE 0x00C8 |
Definition at line 430 of file 9S12XDP512.h.
| #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) |
Definition at line 436 of file 9S12XDP512.h.
| #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) |
Definition at line 437 of file 9S12XDP512.h.
| #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) |
Definition at line 435 of file 9S12XDP512.h.
| #define SCI0BD DVUSP(SCI0_BASE + 0x0) |
Definition at line 432 of file 9S12XDP512.h.
Referenced by initSCIStuff().
| #define SCI0CR1 DVUCP(SCI0_BASE + 0x2) |
Definition at line 433 of file 9S12XDP512.h.
Referenced by initSCIStuff().
| #define SCI0CR2 DVUCP(SCI0_BASE + 0x3) |
Definition at line 439 of file 9S12XDP512.h.
Referenced by checksumAndSend(), initSCIStuff(), main(), resetReceiveState(), and SCI0ISR().
| #define SCI0DRH DVUCP(SCI0_BASE + 0x6) |
Definition at line 442 of file 9S12XDP512.h.
| #define SCI0DRL DVUCP(SCI0_BASE + 0x7) |
Definition at line 443 of file 9S12XDP512.h.
Referenced by checksumAndSend(), SCI0ISR(), and sendAndIncrement().
| #define SCI0SR1 DVUCP(SCI0_BASE + 0x4) |
Definition at line 440 of file 9S12XDP512.h.
Referenced by checksumAndSend(), and SCI0ISR().
| #define SCI0SR2 DVUCP(SCI0_BASE + 0x5) |
Definition at line 441 of file 9S12XDP512.h.
| #define SYNR DVUCP(0x0034) |
Definition at line 228 of file 9S12XDP512.h.
Referenced by initPLL().
| #define TC0 DVUSP(0x0050) |
Definition at line 295 of file 9S12XDP512.h.
Referenced by PrimaryRPMISR().
| #define TC0H DVUSP(0x0078) |
Definition at line 289 of file 9S12XDP512.h.
| #define TC1 DVUSP(0x0052) |
Definition at line 296 of file 9S12XDP512.h.
Referenced by SecondaryRPMISR().
| #define TC1H DVUSP(0x007A) |
Definition at line 290 of file 9S12XDP512.h.
| #define TC2 DVUSP(0x0054) |
Definition at line 297 of file 9S12XDP512.h.
| #define TC2_ADDR AVUSP(0x0054) |
Definition at line 304 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TC2H DVUSP(0x007C) |
Definition at line 291 of file 9S12XDP512.h.
| #define TC3 DVUSP(0x0056) |
Definition at line 298 of file 9S12XDP512.h.
| #define TC3_ADDR AVUSP(0x0056) |
Definition at line 305 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TC3H DVUSP(0x007E) |
Definition at line 292 of file 9S12XDP512.h.
| #define TC4 DVUSP(0x0058) |
Definition at line 299 of file 9S12XDP512.h.
| #define TC4_ADDR AVUSP(0x0058) |
Definition at line 306 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TC5 DVUSP(0x005A) |
Definition at line 300 of file 9S12XDP512.h.
| #define TC5_ADDR AVUSP(0x005A) |
Definition at line 307 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TC6 DVUSP(0x005C) |
Definition at line 301 of file 9S12XDP512.h.
| #define TC6_ADDR AVUSP(0x005C) |
Definition at line 308 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TC7 DVUSP(0x005E) |
Definition at line 302 of file 9S12XDP512.h.
| #define TC7_ADDR AVUSP(0x005E) |
Definition at line 309 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TCNT DVUSP(0x0044) |
Definition at line 245 of file 9S12XDP512.h.
Referenced by InjectorXISR(), main(), PrimaryRPMISR(), RTIISR(), SCI0ISR(), and SecondaryRPMISR().
| #define TCTL1 DVUCP(0x0048) |
Definition at line 268 of file 9S12XDP512.h.
Referenced by changeSyncStatus(), and initECTTimer().
| #define TCTL1_ADDR AVUCP(0x0048) |
Definition at line 270 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TCTL2 DVUCP(0x0049) |
Definition at line 269 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define TCTL2_ADDR AVUCP(0x0049) |
Definition at line 271 of file 9S12XDP512.h.
Referenced by initVariables().
| #define TCTL3 DVUCP(0x004A) |
Definition at line 285 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define TCTL4 DVUCP(0x004B) |
Definition at line 286 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define TFLG DVUCP(0x004E) |
Definition at line 252 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), PrimaryRPMISR(), and SecondaryRPMISR().
| #define TFLGOF DVUCP(0x004F) |
Definition at line 253 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), PrimaryRPMISR(), SecondaryRPMISR(), and TimerOverflow().
| #define TIE DVUCP(0x004C) |
Definition at line 249 of file 9S12XDP512.h.
Referenced by initECTTimer(), InjectorXISR(), and PrimaryRPMISR().
| #define TIOS DVUCP(0x0040) |
Definition at line 248 of file 9S12XDP512.h.
Referenced by changeSyncStatus(), and initECTTimer().
| #define TSCR1 DVUCP(0x0046) |
Definition at line 250 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define TSCR2 DVUCP(0x004D) |
Definition at line 251 of file 9S12XDP512.h.
Referenced by initECTTimer().
| #define TTOV DVUCP(0x0047) |
Definition at line 257 of file 9S12XDP512.h.
| #define VREGAPICL DVUCP(0x02F2) |
Definition at line 812 of file 9S12XDP512.h.
| #define VREGAPIR DVUSP(0x02F4) |
Definition at line 814 of file 9S12XDP512.h.
| #define VREGAPITR DVUCP(0x02F3) |
Definition at line 813 of file 9S12XDP512.h.
| #define VREGCTRL DVUCP(0x02F1) |
Definition at line 811 of file 9S12XDP512.h.
Referenced by initInterrupts(), and LowVoltageISR().
| #define WOMM DVUCP(0x0256) |
Definition at line 135 of file 9S12XDP512.h.
| #define WOMS DVUCP(0x024E) |
Definition at line 124 of file 9S12XDP512.h.
| #define XGCCR DVUCP(0x039D) |
Definition at line 899 of file 9S12XDP512.h.
| #define XGCHID DVUCP(0x0382) |
Definition at line 875 of file 9S12XDP512.h.
| #define XGIF_0 DVUCP(0x0388) |
Definition at line 879 of file 9S12XDP512.h.
| #define XGIF_1 DVUCP(0x0389) |
Definition at line 880 of file 9S12XDP512.h.
| #define XGIF_2 DVUCP(0x038A) |
Definition at line 881 of file 9S12XDP512.h.
| #define XGIF_3 DVUCP(0x038B) |
Definition at line 882 of file 9S12XDP512.h.
| #define XGIF_4 DVUCP(0x038C) |
Definition at line 883 of file 9S12XDP512.h.
| #define XGIF_5 DVUCP(0x038D) |
Definition at line 884 of file 9S12XDP512.h.
| #define XGIF_6 DVUCP(0x038E) |
Definition at line 885 of file 9S12XDP512.h.
| #define XGIF_7 DVUCP(0x038F) |
Definition at line 886 of file 9S12XDP512.h.
| #define XGIF_8 DVUCP(0x0390) |
Definition at line 887 of file 9S12XDP512.h.
| #define XGIF_9 DVUCP(0x0391) |
Definition at line 888 of file 9S12XDP512.h.
| #define XGIF_A DVUCP(0x0392) |
Definition at line 889 of file 9S12XDP512.h.
| #define XGIF_B DVUCP(0x0393) |
Definition at line 890 of file 9S12XDP512.h.
| #define XGIF_C DVUCP(0x0394) |
Definition at line 891 of file 9S12XDP512.h.
| #define XGIF_D DVUCP(0x0395) |
Definition at line 892 of file 9S12XDP512.h.
| #define XGIF_E DVUCP(0x0396) |
Definition at line 893 of file 9S12XDP512.h.
| #define XGIF_F DVUCP(0x0397) |
Definition at line 894 of file 9S12XDP512.h.
| #define XGMCTL DVUSP(0x0380) |
Definition at line 872 of file 9S12XDP512.h.
Referenced by initXgate().
| #define XGMCTLHI DVUCP(0x0380) |
Definition at line 873 of file 9S12XDP512.h.
| #define XGMCTLLO DVUCP(0x0381) |
Definition at line 874 of file 9S12XDP512.h.
| #define XGPC DVUSP(0x039E) |
Definition at line 900 of file 9S12XDP512.h.
| #define XGR1 DVUSP(0x03A2) |
Definition at line 902 of file 9S12XDP512.h.
| #define XGR2 DVUSP(0x03A4) |
Definition at line 904 of file 9S12XDP512.h.
| #define XGR3 DVUSP(0x03A6) |
Definition at line 906 of file 9S12XDP512.h.
| #define XGR4 DVUSP(0x03A8) |
Definition at line 908 of file 9S12XDP512.h.
| #define XGR5 DVUSP(0x03AA) |
Definition at line 910 of file 9S12XDP512.h.
| #define XGR6 DVUSP(0x03AC) |
Definition at line 912 of file 9S12XDP512.h.
| #define XGR7 DVUSP(0x03AE) |
Definition at line 914 of file 9S12XDP512.h.
| #define XGSEM DVUSP(0x039A) |
Definition at line 897 of file 9S12XDP512.h.
| #define XGSWT DVUSP(0x0398) |
Definition at line 895 of file 9S12XDP512.h.
Referenced by RTIISR().
| #define XGVBR DVUSP(0x0386) |
Definition at line 878 of file 9S12XDP512.h.
Referenced by initXgate().
